global_store_async_from_lds_b32 GPU Native ISA AMD Vector

Vector/Global Memory

global_store_async_from_lds_b32

AMDGPU GLOBAL vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
unassigned
63
VSRC
62:55
TH
54:52
SCOPE
51:50
SVE
49
SCALE_OFFSET
48
unassigned
47:40
VDST
39:32
11101110
31:24
unassigned
23:22
01100100
21:14
unassigned
13:8
NV
7
SADDR
6:0
 

The ENC_VGLOBAL layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 100 in OP rebuilds 0x0000000000000000EE190000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format GLOBAL
Width 96 bits
Opcode 100
Identifier 0x0000000000000000EE190000

Operands

  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VSRC
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. Any scalar GPR operand including VCC and NULL. Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VGLOBAL encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Sources