global_store_dword GPU Native ISA AMD Vector

GLOBAL STORE DWORD Vector/Global Memory

global_store_dword VADDR, VDATA, SADDR, offset

Store one 32-bit dword per lane to the global address space using a 64-bit per-lane address.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (GLOBAL) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format GLOBAL
Width 32 bits
Execution Unit Vector Memory Unit
Register Classes VGPR, SGPR
Memory Segment global

Operands

  • VADDR
    Per-lane 64-bit address (VGPR pair)
  • VDATA
    Per-lane value to store (VGPR)
  • SADDR
    Optional uniform base (SGPR pair)
  • offset
    Immediate offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Global-Memory Store ↗
equivalent with restrictions
st (PTX)

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Description

Store 32 bits of data from vector input registers into the global aperture.

Semantics

*(VADDR[lane] + SADDR + offset) = VDATA[lane] for each active lane.

Example

global_store_dword  v[0:1], v2, off   // *(v[0:1]) = v2 per lane

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources