Global-Memory Store Memory
Write a register value to the device's global memory address space.
Vendor-Neutral Definition
*addr = src, where addr resolves in the global address space.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both write a register value to device global memory.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | st | global_store_dword |
| ISA Layer | Virtual | Native |
| Data Types | b16, b32, b64, b8, f16, f32, f64, s16, s32, s64, s8, u16, u32, u64, u8 | — |
| Version / Target Introduced | PTX ISA 1.0 | gfx942/gfx1100 |
Important Differences
- As with global loads, AMDGPU splits global-memory stores across global_*/flat_*/buffer_* families with different addressing behavior.
Source Evidence
- Parallel Thread Execution ISA ↗ — NVIDIA Corporation
- User Guide for AMDGPU Backend ↗ — LLVM Project
Verification method: documentation