AMDGPU / GFX Instructions GPU Native ISA AMD
2442 instructions - showing 100 per page, page 15 of 25 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
How AMDGPU compares to the other GPU ISA
Decode a AMDGPU instruction word
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| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| v_cmp_lt_i16 | v_cmp_lt_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_lt_i32 | v_cmp_lt_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_lt_i64 | v_cmp_lt_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_lt_u16 | v_cmp_lt_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_lt_u32 | v_cmp_lt_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_lt_u64 | v_cmp_lt_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ne_i16 | v_cmp_ne_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ne_i32 | v_cmp_ne_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ne_i64 | v_cmp_ne_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ne_u16 | v_cmp_ne_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ne_u32 | v_cmp_ne_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ne_u64 | v_cmp_ne_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_neq_f16 | v_cmp_neq_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_neq_f32 | v_cmp_neq_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_neq_f64 | v_cmp_neq_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_nge_f16 | v_cmp_nge_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. | |
| v_cmp_nge_f32 | v_cmp_nge_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. | |
| v_cmp_nge_f64 | v_cmp_nge_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. | |
| v_cmp_ngt_f16 | v_cmp_ngt_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ngt_f32 | v_cmp_ngt_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ngt_f64 | v_cmp_ngt_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_nle_f16 | v_cmp_nle_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. | |
| v_cmp_nle_f32 | v_cmp_nle_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. | |
| v_cmp_nle_f64 | v_cmp_nle_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. | |
| v_cmp_nlg_f16 | v_cmp_nlg_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. | |
| v_cmp_nlg_f32 | v_cmp_nlg_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. | |
| v_cmp_nlg_f64 | v_cmp_nlg_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. | |
| v_cmp_nlt_f16 | v_cmp_nlt_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_nlt_f32 | v_cmp_nlt_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_nlt_f64 | v_cmp_nlt_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_o_f16 | v_cmp_o_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_o_f32 | v_cmp_o_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_o_f64 | v_cmp_o_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_t_f16 | v_cmp_t_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | |
| v_cmp_t_f32 | v_cmp_t_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | |
| v_cmp_t_f64 | v_cmp_t_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | |
| v_cmp_t_i16 | v_cmp_t_i16 | VOPC | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | ||
| v_cmp_t_i32 | v_cmp_t_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | |
| v_cmp_t_i64 | v_cmp_t_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | |
| v_cmp_t_u16 | v_cmp_t_u16 | VOPC | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | ||
| v_cmp_t_u32 | v_cmp_t_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | |
| v_cmp_t_u64 | v_cmp_t_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | |
| v_cmp_tru_f16 | v_cmp_tru_f16 | VOPC | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | ||
| v_cmp_tru_f32 | v_cmp_tru_f32 | VOPC | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | ||
| v_cmp_tru_f64 | v_cmp_tru_f64 | VOPC | Set the per-lane condition code to 1. Store the result into VCC or a scalar register. | ||
| v_cmp_u_f16 | v_cmp_u_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_u_f32 | v_cmp_u_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_u_f64 | v_cmp_u_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register. | |
| v_cmps_eq_f32 | v_cmps_eq_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_eq_f64 | v_cmps_eq_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_f_f32 | v_cmps_f_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_f_f64 | v_cmps_f_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_ge_f32 | v_cmps_ge_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_ge_f64 | v_cmps_ge_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_gt_f32 | v_cmps_gt_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_gt_f64 | v_cmps_gt_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_le_f32 | v_cmps_le_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_le_f64 | v_cmps_le_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_lg_f32 | v_cmps_lg_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_lg_f64 | v_cmps_lg_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_lt_f32 | v_cmps_lt_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_lt_f64 | v_cmps_lt_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_neq_f32 | v_cmps_neq_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_neq_f64 | v_cmps_neq_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_nge_f32 | v_cmps_nge_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_nge_f64 | v_cmps_nge_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_ngt_f32 | v_cmps_ngt_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_ngt_f64 | v_cmps_ngt_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_nle_f32 | v_cmps_nle_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_nle_f64 | v_cmps_nle_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_nlg_f32 | v_cmps_nlg_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_nlg_f64 | v_cmps_nlg_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_nlt_f32 | v_cmps_nlt_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_nlt_f64 | v_cmps_nlt_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_o_f32 | v_cmps_o_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_o_f64 | v_cmps_o_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_tru_f32 | v_cmps_tru_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_tru_f64 | v_cmps_tru_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_u_f32 | v_cmps_u_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmps_u_f64 | v_cmps_u_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_eq_f32 | v_cmpsx_eq_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_eq_f64 | v_cmpsx_eq_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_f_f32 | v_cmpsx_f_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_f_f64 | v_cmpsx_f_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_ge_f32 | v_cmpsx_ge_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_ge_f64 | v_cmpsx_ge_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_gt_f32 | v_cmpsx_gt_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_gt_f64 | v_cmpsx_gt_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_le_f32 | v_cmpsx_le_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_le_f64 | v_cmpsx_le_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_lg_f32 | v_cmpsx_lg_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_lg_f64 | v_cmpsx_lg_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_lt_f32 | v_cmpsx_lt_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_lt_f64 | v_cmpsx_lt_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_neq_f32 | v_cmpsx_neq_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_neq_f64 | v_cmpsx_neq_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_nge_f32 | v_cmpsx_nge_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_nge_f64 | v_cmpsx_nge_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_ngt_f32 | v_cmpsx_ngt_f32 | VOPC | AMDGPU VOPC vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cmpsx_ngt_f64 | v_cmpsx_ngt_f64 | VOPC | AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗