AMDGPU / GFX Instructions GPU Native ISA AMD
1960 instructions - showing 100 per page, page 15 of 20 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| v_cvt_scalef32_pk_bf8_f16 | v_cvt_scalef32_pk_bf8_f16 | VOP3 | Scale a packed 2-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values… | ||
| v_cvt_scalef32_pk_bf8_f32 | v_cvt_scalef32_pk_bf8_f32 | VOP3 | Scale two single-precision float inputs using the exponent provided by the third single-precision float input, then convert the values to a packed… | ||
| v_cvt_scalef32_pk_f16_bf8 | v_cvt_scalef32_pk_f16_bf8 | VOP3 | Convert from a packed 2-component BF8 float input to a packed half-precision float value, then scale the packed values using the exponent provided by… | ||
| v_cvt_scalef32_pk_f16_fp4 | v_cvt_scalef32_pk_f16_fp4 | VOP3 | Convert from a packed 2-component FP4 float input to a packed half-precision float value, then scale the packed values using the exponent provided by… | ||
| v_cvt_scalef32_pk_f16_fp8 | v_cvt_scalef32_pk_f16_fp8 | VOP3 | Convert from a packed 2-component FP8 float input to a packed half-precision float value, then scale the packed values using the exponent provided by… | ||
| v_cvt_scalef32_pk_f32_bf8 | v_cvt_scalef32_pk_f32_bf8 | VOP3 | Convert from a packed 2-component BF8 float input to a packed single-precision float value, then scale the packed values using the exponent provided… | ||
| v_cvt_scalef32_pk_f32_fp4 | v_cvt_scalef32_pk_f32_fp4 | VOP3 | Convert from a packed 2-component FP4 float input to a packed single-precision float value, then scale the packed values using the exponent provided… | ||
| v_cvt_scalef32_pk_f32_fp8 | v_cvt_scalef32_pk_f32_fp8 | VOP3 | Convert from a packed 2-component FP8 float input to a packed single-precision float value, then scale the packed values using the exponent provided… | ||
| v_cvt_scalef32_pk_fp4_bf16 | v_cvt_scalef32_pk_fp4_bf16 | VOP3 | Scale a packed 2-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a… | ||
| v_cvt_scalef32_pk_fp4_f16 | v_cvt_scalef32_pk_fp4_f16 | VOP3 | Scale a packed 2-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values… | ||
| v_cvt_scalef32_pk_fp4_f32 | v_cvt_scalef32_pk_fp4_f32 | VOP3 | Scale two single-precision float inputs using the exponent provided by the third single-precision float input, then convert the values to a packed… | ||
| v_cvt_scalef32_pk_fp8_bf16 | v_cvt_scalef32_pk_fp8_bf16 | VOP3 | Scale a packed 2-component BF16 float input using the exponent provided by the second single-precision float input, then convert the values to a… | ||
| v_cvt_scalef32_pk_fp8_f16 | v_cvt_scalef32_pk_fp8_f16 | VOP3 | Scale a packed 2-component half-precision float input using the exponent provided by the second single-precision float input, then convert the values… | ||
| v_cvt_scalef32_pk_fp8_f32 | v_cvt_scalef32_pk_fp8_f32 | VOP3 | Scale two single-precision float inputs using the exponent provided by the third single-precision float input, then convert the values to a packed… | ||
| v_cvt_scalef32_sr_bf8_bf16 | v_cvt_scalef32_sr_bf8_bf16 | VOP3 | Scale a BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float value with… | ||
| v_cvt_scalef32_sr_bf8_f16 | v_cvt_scalef32_sr_bf8_f16 | VOP3 | Scale a half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float… | ||
| v_cvt_scalef32_sr_bf8_f32 | v_cvt_scalef32_sr_bf8_f32 | VOP3 | Scale a single-precision float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float… | ||
| v_cvt_scalef32_sr_fp8_bf16 | v_cvt_scalef32_sr_fp8_bf16 | VOP3 | Scale a BF16 float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float value with… | ||
| v_cvt_scalef32_sr_fp8_f16 | v_cvt_scalef32_sr_fp8_f16 | VOP3 | Scale a half-precision float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float… | ||
| v_cvt_scalef32_sr_fp8_f32 | v_cvt_scalef32_sr_fp8_f32 | VOP3 | Scale a single-precision float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float… | ||
| v_cvt_scalef32_sr_pk16_bf6_bf16 | v_cvt_scalef32_sr_pk16_bf6_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk16_bf6_f16 | v_cvt_scalef32_sr_pk16_bf6_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk16_bf6_f32 | v_cvt_scalef32_sr_pk16_bf6_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk16_fp6_bf16 | v_cvt_scalef32_sr_pk16_fp6_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk16_fp6_f16 | v_cvt_scalef32_sr_pk16_fp6_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk16_fp6_f32 | v_cvt_scalef32_sr_pk16_fp6_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk32_bf6_bf16 | v_cvt_scalef32_sr_pk32_bf6_bf16 | VOP3 | Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a… | ||
| v_cvt_scalef32_sr_pk32_bf6_f16 | v_cvt_scalef32_sr_pk32_bf6_f16 | VOP3 | Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values… | ||
| v_cvt_scalef32_sr_pk32_bf6_f32 | v_cvt_scalef32_sr_pk32_bf6_f32 | VOP3 | Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the… | ||
| v_cvt_scalef32_sr_pk32_fp6_bf16 | v_cvt_scalef32_sr_pk32_fp6_bf16 | VOP3 | Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a… | ||
| v_cvt_scalef32_sr_pk32_fp6_f16 | v_cvt_scalef32_sr_pk32_fp6_f16 | VOP3 | Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values… | ||
| v_cvt_scalef32_sr_pk32_fp6_f32 | v_cvt_scalef32_sr_pk32_fp6_f32 | VOP3 | Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the… | ||
| v_cvt_scalef32_sr_pk8_bf8_bf16 | v_cvt_scalef32_sr_pk8_bf8_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk8_bf8_f16 | v_cvt_scalef32_sr_pk8_bf8_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk8_bf8_f32 | v_cvt_scalef32_sr_pk8_bf8_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk8_fp4_bf16 | v_cvt_scalef32_sr_pk8_fp4_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk8_fp4_f16 | v_cvt_scalef32_sr_pk8_fp4_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk8_fp4_f32 | v_cvt_scalef32_sr_pk8_fp4_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk8_fp8_bf16 | v_cvt_scalef32_sr_pk8_fp8_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk8_fp8_f16 | v_cvt_scalef32_sr_pk8_fp8_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk8_fp8_f32 | v_cvt_scalef32_sr_pk8_fp8_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scalef32_sr_pk_fp4_bf16 | v_cvt_scalef32_sr_pk_fp4_bf16 | VOP3 | Scale a packed 2-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a… | ||
| v_cvt_scalef32_sr_pk_fp4_f16 | v_cvt_scalef32_sr_pk_fp4_f16 | VOP3 | Scale a packed 2-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values… | ||
| v_cvt_sr_bf16_f32 | v_cvt_sr_bf16_f32 | VOP3 | Convert from a single-precision float input to a BF16 value with stochastic rounding using seed data from the second input. | ||
| v_cvt_sr_bf8_f16 | v_cvt_sr_bf8_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_sr_bf8_f32 | v_cvt_sr_bf8_f32 | VOP3 | Convert from a single-precision float input to a BF8 value with stochastic rounding using seed data from the second input. | ||
| v_cvt_sr_bf8_f32_gfx12 | v_cvt_sr_bf8_f32_gfx12 | VOP3 | gfx1100 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| v_cvt_sr_f16_f32 | v_cvt_sr_f16_f32 | VOP3 | Convert from a single-precision float input to a half-precision value with stochastic rounding using seed data from the second input. | ||
| v_cvt_sr_fp8_f16 | v_cvt_sr_fp8_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_sr_fp8_f32 | v_cvt_sr_fp8_f32 | VOP3 | Convert from a single-precision float input to an FP8 value with stochastic rounding using seed data from the second input. | ||
| v_cvt_sr_fp8_f32_gfx12 | v_cvt_sr_fp8_f32_gfx12 | VOP3 | gfx1100 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| v_cvt_sr_fp8_f32_gfx1250 | v_cvt_sr_fp8_f32_gfx1250 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_sr_pk_bf16_f32 | v_cvt_sr_pk_bf16_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_sr_pk_f16_f32 | v_cvt_sr_pk_f16_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_u16_f16 | v_cvt_u16_f16 | VOP1 | gfx1100 | Convert from a half-precision float input to an unsigned 16-bit integer value and store the result into a vector register. | |
| v_cvt_u32_f32 | v_cvt_u32_f32 | VOP1 | gfx1100 | Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a vector register. | |
| v_cvt_u32_f64 | v_cvt_u32_f64 | VOP1 | gfx1100 | Convert from a double-precision float input to an unsigned 32-bit integer value and store the result into a vector register. | |
| v_cvt_u32_u16 | v_cvt_u32_u16 | VOP1 | gfx1100 | Convert from an unsigned 16-bit integer input to an unsigned 32-bit integer value using zero extension and store the result into a vector register. | |
| v_div_fixup_f16 | v_div_fixup_f16 | VOP3 | gfx1100 | Given a half-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply… | |
| v_div_fixup_f16_gfx9 | v_div_fixup_f16_gfx9 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_div_fixup_f32 | v_div_fixup_f32 | VOP3 | gfx1100 | Given a single-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply… | |
| v_div_fixup_f64 | v_div_fixup_f64 | VOP3 | gfx1100 | Given a double-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply… | |
| v_div_fixup_legacy_f16 | v_div_fixup_legacy_f16 | VOP3 | Half precision division fixup. Has non-standard rule for OPSEL. | ||
| v_div_fmas_f32 | v_div_fmas_f32 | VOP3 | gfx1100 | Multiply two single-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if… | |
| v_div_fmas_f64 | v_div_fmas_f64 | VOP3 | gfx1100 | Multiply two double-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if… | |
| v_div_scale_f32 | v_div_scale_f32 | VOP3 | gfx1100 | Given a single-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the… | |
| v_div_scale_f64 | v_div_scale_f64 | VOP3 | gfx1100 | Given a double-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the… | |
| v_dot2_bf16_bf16 | v_dot2_bf16_bf16 | VOP3 | gfx1100 | Compute the dot product of two packed 2-D BF16 float inputs, add the third input and store the result into a vector register. | |
| v_dot2_f16_f16 | v_dot2_f16_f16 | VOP3 | gfx1100 | Compute the dot product of two packed 2-D half-precision float inputs, add the third input and store the result into a vector register. | |
| v_dot2_i32_i16 | v_dot2_i32_i16 | VOP3P | Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from… | ||
| v_dot2_u32_u16 | v_dot2_u32_u16 | VOP3P | Compute the dot product of two packed 2-D unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value… | ||
| v_dot2c_f32_bf16 | v_dot2c_f32_bf16 | VOP2 | Compute the dot product of two packed 2-D BF16 float inputs in the single-precision float domain and accumulate with the single-precision float value… | ||
| v_dot2c_f32_f16 | v_dot2c_f32_f16 | VOP2 | Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate with the single-precision… | ||
| v_dot2c_i32_i16 | v_dot2c_i32_i16 | VOP2 | Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit… | ||
| v_dot4_f32_bf8_bf8 | v_dot4_f32_bf8_bf8 | VOP3P | gfx1100 | Compute the dot product of two packed 4-D BF8 float inputs in the single-precision float domain, add a single-precision float value from the third… | |
| v_dot4_f32_bf8_fp8 | v_dot4_f32_bf8_fp8 | VOP3P | gfx1100 | Compute the dot product of a packed 4-D BF8 float input and a packed 4-D FP8 float input in the single-precision float domain, add a single-precision… | |
| v_dot4_f32_fp8_bf8 | v_dot4_f32_fp8_bf8 | VOP3P | gfx1100 | Compute the dot product of a packed 4-D FP8 float input and a packed 4-D BF8 float input in the single-precision float domain, add a single-precision… | |
| v_dot4_f32_fp8_fp8 | v_dot4_f32_fp8_fp8 | VOP3P | gfx1100 | Compute the dot product of two packed 4-D FP8 float inputs in the single-precision float domain, add a single-precision float value from the third… | |
| v_dot4_i32_i8 | v_dot4_i32_i8 | VOP3P | gfx1100 | Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the… | |
| v_dot4_i32_iu8 | v_dot4_i32_iu8 | VOP3P | gfx1100 | Compute the dot product of two packed 4-D signed or unsigned 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer… | |
| v_dot4_u32_u8 | v_dot4_u32_u8 | VOP3P | gfx1100 | Compute the dot product of two packed 4-D unsigned 8-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value… | |
| v_dot4c_i32_i8 | v_dot4c_i32_i8 | VOP2 | Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit… | ||
| v_dot8_i32_i4 | v_dot8_i32_i4 | VOP3P | gfx1100 | Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the… | |
| v_dot8_i32_iu4 | v_dot8_i32_iu4 | VOP3P | gfx1100 | Compute the dot product of two packed 8-D signed or unsigned 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer… | |
| v_dot8_u32_u4 | v_dot8_u32_u4 | VOP3P | gfx1100 | Compute the dot product of two packed 8-D unsigned 4-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value… | |
| v_dot8c_i32_i4 | v_dot8c_i32_i4 | VOP2 | Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit… | ||
| v_exp_bf16 | v_exp_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_exp_f16 | v_exp_f16 | VOP1 | Calculate 2 raised to the power of the half-precision float input and store the result into a vector register. | ||
| v_exp_f32 | v_exp_f32 | VOP1 | gfx1100 | Calculate 2 raised to the power of the single-precision float input and store the result into a vector register. | |
| v_exp_legacy_f32 | v_exp_legacy_f32 | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_ffbh_i32 | v_ffbh_i32 | VOP1 | Count the number of leading bits that are the same as the sign bit of a vector input and store the result into a vector register. | ||
| v_ffbh_u32 | v_ffbh_u32 | VOP1 | Count the number of leading "0" bits before the first "1" in a vector input and store the result into a vector register. | ||
| v_ffbl_b32 | v_ffbl_b32 | VOP1 | Count the number of trailing "0" bits before the first "1" in a vector input and store the result into a vector register. | ||
| v_floor_f16 | v_floor_f16 | VOP1 | Round the half-precision float input down to previous integer and store the result in floating point format into a vector register. | ||
| v_floor_f32 | v_floor_f32 | VOP1 | gfx1100 | Round the single-precision float input down to previous integer and store the result in floating point format into a vector register. | |
| v_floor_f64 | v_floor_f64 | VOP1 | gfx1100 | Round the double-precision float input down to previous integer and store the result in floating point format into a vector register. | |
| v_fma_dx9_zero_f32 | v_fma_dx9_zero_f32 | VOP3 | gfx1100 | Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0. | |
| v_fma_f16 | v_fma_f16 | VOP3 | gfx1100 | Multiply two half-precision float inputs and add a third input using fused multiply add, and store the result into a vector register. | |
| v_fma_f16_gfx9 | v_fma_f16_gfx9 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_fma_f32 | v_fma_f32 VDST, S0, S1, S2 | VOP3 | gfx942, gfx1100 | Vector ALU | Per-lane single-precision fused multiply-add. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗