v_cmp_nlg_f32 GPU Native ISA AMD Vector

Comparison

v_cmp_nlg_f32

Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input.

Encoding

Binary Layout (AMD CDNA 5)
0111110
31:25
00011010
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 26 in OP rebuilds 0x7C340000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 74), AMD CDNA 3 (opcode 74), AMD CDNA 2 (opcode 74), AMD CDNA 1 (opcode 74), AMD RDNA 2 (opcode 10), AMD RDNA 1 (opcode 10). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format VOPC
Width 32 bits
Opcode 26
Identifier 0x7C340000

Operands

  • vcc
    Written. Written in the assembly; this encoding has no field for it. 64-bit vector condition code. Data format: 64-bit mask value, read or written to a consecutive run of GPRs. The first GPR contains the least significant dword of the data. This format is generally used for lane masks and may be truncated to 32 bits when running in wave32 mode. Scalar operands with the M64 format do not have an alignment restriction when running in wave32 mode. (OPR_VCC, FMT_NUM_M64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOPC encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Description

Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. Store the result into VCC or a scalar register.

Semantics

D0.u64[laneId] = !(S0.f32 <> S1.f32); // With NAN inputs this is not the same operation as == // D0 = VCC in VOPC encoding.

Example

v_cmp_nlg_f32 vcc, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources