v_cmp_t_f16 GPU Native ISA AMD Vector

Comparison

v_cmp_t_f16

Set the per-lane condition code to 1. Store the result into VCC or a scalar register.

Also written as v_cmp_tru_f16. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 3.5)
0111110
31:25
00001111
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 15 in OP rebuilds 0x7C1E0000, an identifier AMD lists for this encoding. The same in AMD RDNA 3.

Format VOPC
Width 32 bits
Opcode 15
Identifier 0x7C1E0000

Operands

  • vcc
    Written. Written in the assembly; this encoding has no field for it. 64-bit vector condition code. Data format: 64-bit mask value, read or written to a consecutive run of GPRs. The first GPR contains the least significant dword of the data. This format is generally used for lane masks and may be truncated to 32 bits when running in wave32 mode. Scalar operands with the M64 format do not have an alignment restriction when running in wave32 mode. (OPR_VCC, FMT_NUM_M64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. (OPR_SRC, FMT_NUM_F16)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16-bit half-precision floating point value. (OPR_VGPR, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOPC encoding (AMD RDNA 3.5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Example

v_cmp_t_f16 vcc, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources