v_cmpsx_neq_f64 GPU Native ISA AMD Vector

Comparison

v_cmpsx_neq_f64

AMDGPU VOPC vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOPC) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOPC

Operands

  • 1: special register
    Architectural register rather than a general-purpose one. Written vcc in the assembler example.
  • 2: immediate
    Literal value encoded in the instruction. Written 0 in the assembler example.
  • 3: VGPR range
    Consecutive vector registers holding a wider value. Written v[2:3] in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Example

v_cmpsx_neq_f64 vcc, 0, v[2:3]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_vopc.s). Not from an AMD document, and not authored here.

Sources