AMDGPU / GFX Instructions GPU Native ISA AMD
2442 instructions - showing 100 per page, page 17 of 25 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
How AMDGPU compares to the other GPU ISA
Decode a AMDGPU instruction word
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| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| v_cmpx_t_f32 | v_cmpx_t_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask. | |
| v_cmpx_t_f64 | v_cmpx_t_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask. | |
| v_cmpx_t_i16 | v_cmpx_t_i16 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_t_i32 | v_cmpx_t_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | |
| v_cmpx_t_i64 | v_cmpx_t_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | |
| v_cmpx_t_u16 | v_cmpx_t_u16 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_t_u32 | v_cmpx_t_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | |
| v_cmpx_t_u64 | v_cmpx_t_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | |
| v_cmpx_tru_f16 | v_cmpx_tru_f16 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_tru_f32 | v_cmpx_tru_f32 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_tru_f64 | v_cmpx_tru_f64 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_u_f16 | v_cmpx_u_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not orderable to the second input. | |
| v_cmpx_u_f32 | v_cmpx_u_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not orderable to the second input. | |
| v_cmpx_u_f64 | v_cmpx_u_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not orderable to the second input. | |
| v_cndmask_b16 | v_cndmask_b16 | VOP3 | gfx1100 | Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register. | |
| v_cndmask_b16_fake16 | v_cndmask_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cndmask_b16_t16 | v_cndmask_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cndmask_b32 | v_cndmask_b32 | VOP2 | gfx1100 | Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register. | |
| v_cos_bf16 | v_cos_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cos_f16 | v_cos_f16 | VOP1 | gfx1100 | Calculate the trigonometric cosine of a half-precision float value using IEEE rules and store the result into a vector register. | |
| v_cos_f32 | v_cos_f32 | VOP1 | gfx1100 | Calculate the trigonometric cosine of a single-precision float value using IEEE rules and store the result into a vector register. | |
| v_cubeid_f32 | v_cubeid_f32 | VOP3 | gfx1100 | Compute the cubemap face ID of a 3D coordinate specified as three single-precision float inputs. | |
| v_cubema_f32 | v_cubema_f32 | VOP3 | gfx1100 | Compute the cubemap major axis of a 3D coordinate specified as three single-precision float inputs. | |
| v_cubesc_f32 | v_cubesc_f32 | VOP3 | gfx1100 | Compute the cubemap S coordinate of a 3D coordinate specified as three single-precision float inputs. | |
| v_cubetc_f32 | v_cubetc_f32 | VOP3 | gfx1100 | Compute the cubemap T coordinate of a 3D coordinate specified as three single-precision float inputs. | |
| v_cvt_f16_bf8 | v_cvt_f16_bf8 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f16_f32 | v_cvt_f16_f32 | VOP1 | gfx1100 | Convert from a single-precision float input to a half-precision float value and store the result into a vector register. | |
| v_cvt_f16_f32_fake16 | v_cvt_f16_f32_fake16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f16_f32_t16 | v_cvt_f16_f32_t16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f16_fp8 | v_cvt_f16_fp8 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f16_i16 | v_cvt_f16_i16 | VOP1 | gfx1100 | Convert from a signed 16-bit integer input to a half-precision float value and store the result into a vector register. | |
| v_cvt_f16_u16 | v_cvt_f16_u16 | VOP1 | gfx1100 | Convert from an unsigned 16-bit integer input to a half-precision float value and store the result into a vector register. | |
| v_cvt_f32_bf16 | v_cvt_f32_bf16 | VOP1 | Convert from a BF16 float input to a single-precision float value and store the result into a vector register. | ||
| v_cvt_f32_bf8 | v_cvt_f32_bf8 | VOP1 | gfx1100 | Convert from a BF8 float input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_bf8_op_sel | v_cvt_f32_bf8_op_sel | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f32_f16 | v_cvt_f32_f16 | VOP1 | gfx1100 | Convert from a half-precision float input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_f16_fake16 | v_cvt_f32_f16_fake16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f32_f16_t16 | v_cvt_f32_f16_t16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f32_f64 | v_cvt_f32_f64 | VOP1 | gfx1100 | Convert from a double-precision float input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_fp8 | v_cvt_f32_fp8 | VOP1 | gfx1100 | Convert from an FP8 float input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_fp8_gfx1250 | v_cvt_f32_fp8_gfx1250 | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f32_fp8_op_sel | v_cvt_f32_fp8_op_sel | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f32_i32 | v_cvt_f32_i32 VDST, S0 | VOP1 | gfx942, gfx1100 | Vector ALU | Per-lane conversion from signed 32-bit integer to single-precision float. |
| v_cvt_f32_u32 | v_cvt_f32_u32 | VOP1 | gfx1100 | Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_ubyte0 | v_cvt_f32_ubyte0 | VOP1 | gfx1100 | Convert an unsigned byte in byte 0 of the input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_ubyte1 | v_cvt_f32_ubyte1 | VOP1 | gfx1100 | Convert an unsigned byte in byte 1 of the input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_ubyte2 | v_cvt_f32_ubyte2 | VOP1 | gfx1100 | Convert an unsigned byte in byte 2 of the input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_ubyte3 | v_cvt_f32_ubyte3 | VOP1 | gfx1100 | Convert an unsigned byte in byte 3 of the input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f64_f32 | v_cvt_f64_f32 | VOP1 | gfx1100 | Convert from a single-precision float input to a double-precision float value and store the result into a vector register. | |
| v_cvt_f64_i32 | v_cvt_f64_i32 | VOP1 | gfx1100 | Convert from a signed 32-bit integer input to a double-precision float value and store the result into a vector register. | |
| v_cvt_f64_u32 | v_cvt_f64_u32 | VOP1 | gfx1100 | Convert from an unsigned 32-bit integer input to a double-precision float value and store the result into a vector register. | |
| v_cvt_flr_i32_f32 | v_cvt_flr_i32_f32 | VOP1 | Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store… | ||
| v_cvt_i16_f16 | v_cvt_i16_f16 | VOP1 | gfx1100 | Convert from a half-precision float input to a signed 16-bit integer value and store the result into a vector register. | |
| v_cvt_i32_f32 | v_cvt_i32_f32 | VOP1 | gfx1100 | Convert from a single-precision float input to a signed 32-bit integer value and store the result into a vector register. | |
| v_cvt_i32_f64 | v_cvt_i32_f64 | VOP1 | gfx1100 | Convert from a double-precision float input to a signed 32-bit integer value and store the result into a vector register. | |
| v_cvt_i32_i16 | v_cvt_i32_i16 | VOP1 | gfx1100 | Convert from a signed 16-bit integer input to a signed 32-bit integer value using sign extension and store the result into a vector register. | |
| v_cvt_norm_i16_f16 | v_cvt_norm_i16_f16 | VOP1 | gfx1100 | Convert from a half-precision float input to a signed normalized short and store the result into a vector register. | |
| v_cvt_norm_u16_f16 | v_cvt_norm_u16_f16 | VOP1 | gfx1100 | Convert from a half-precision float input to an unsigned normalized short and store the result into a vector register. | |
| v_cvt_off_f32_i4 | v_cvt_off_f32_i4 | VOP1 | gfx1100 | Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register. | |
| v_cvt_pk_bf16_f32 | v_cvt_pk_bf16_f32 | VOP3 | Convert from two single-precision float inputs to a packed BF16 value and store the result into a vector register. | ||
| v_cvt_pk_bf8_f16 | v_cvt_pk_bf8_f16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_pk_bf8_f32 | v_cvt_pk_bf8_f32 | VOP3 | gfx1100 | Convert from two single-precision float inputs to a packed BF8 float value with round to nearest even semantics and store the result into 16 bits of… | |
| v_cvt_pk_f16_bf8 | v_cvt_pk_f16_bf8 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_pk_f16_f32 | v_cvt_pk_f16_f32 | VOP3 | Convert from two single-precision float inputs to a packed half-precision value and store the result into a vector register. | ||
| v_cvt_pk_f16_fp8 | v_cvt_pk_f16_fp8 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_pk_f32_bf8 | v_cvt_pk_f32_bf8 | VOP1 | Convert from a packed 2-component BF8 float input to a packed single-precision float value and store the result into a vector register. | ||
| v_cvt_pk_f32_bf8_fake16 | v_cvt_pk_f32_bf8_fake16 | VOP1 | gfx1100 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| v_cvt_pk_f32_bf8_t16 | v_cvt_pk_f32_bf8_t16 | VOP1 | gfx1100 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| v_cvt_pk_f32_fp8 | v_cvt_pk_f32_fp8 | VOP1 | Convert from a packed 2-component FP8 float input to a packed single-precision float value and store the result into a vector register. | ||
| v_cvt_pk_f32_fp8_fake16 | v_cvt_pk_f32_fp8_fake16 | VOP1 | gfx1100 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| v_cvt_pk_f32_fp8_t16 | v_cvt_pk_f32_fp8_t16 | VOP1 | gfx1100 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| v_cvt_pk_fp8_f16 | v_cvt_pk_fp8_f16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_pk_fp8_f32 | v_cvt_pk_fp8_f32 | VOP3 | gfx1100 | Convert from two single-precision float inputs to a packed FP8 float value with round to nearest even semantics and store the result into 16 bits of… | |
| v_cvt_pk_fp8_f32_gfx1250 | v_cvt_pk_fp8_f32_gfx1250 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_pk_i16_f32 | v_cvt_pk_i16_f32 | VOP3 | gfx1100 | Convert two single-precision float inputs into a packed signed 16-bit integer value and store the result into a vector register. | |
| v_cvt_pk_i16_i32 | v_cvt_pk_i16_i32 | VOP2 | gfx1100 | Convert from two signed 32-bit integer inputs to a packed signed 16-bit integer value and store the result into a vector register. | |
| v_cvt_pk_norm_i16_f16 | v_cvt_pk_norm_i16_f16 | VOP3 | gfx1100 | Convert from two half-precision float inputs to a packed signed normalized short and store the result into a vector register. | |
| v_cvt_pk_norm_i16_f32 | v_cvt_pk_norm_i16_f32 | VOP3 | gfx1100 | Convert from two single-precision float inputs to a packed signed normalized short and store the result into a vector register. | |
| v_cvt_pk_norm_u16_f16 | v_cvt_pk_norm_u16_f16 | VOP3 | gfx1100 | Convert from two half-precision float inputs to a packed unsigned normalized short and store the result into a vector register. | |
| v_cvt_pk_norm_u16_f32 | v_cvt_pk_norm_u16_f32 | VOP3 | gfx1100 | Convert from two single-precision float inputs to a packed unsigned normalized short and store the result into a vector register. | |
| v_cvt_pk_u16_f32 | v_cvt_pk_u16_f32 | VOP3 | gfx1100 | Convert two single-precision float inputs into a packed unsigned 16-bit integer value and store the result into a vector register. | |
| v_cvt_pk_u16_u32 | v_cvt_pk_u16_u32 | VOP2 | gfx1100 | Convert from two unsigned 32-bit integer inputs to a packed unsigned 16-bit integer value and store the result into a vector register. | |
| v_cvt_pk_u8_f32 | v_cvt_pk_u8_f32 | VOP3 | gfx1100 | Convert a single-precision float value from the first input to an unsigned 8-bit integer value and pack the result into one byte of the third input… | |
| v_cvt_pkaccum_u8_f32 | v_cvt_pkaccum_u8_f32 | VOP2 | Convert a single-precision float value in the first input to an unsigned 8-bit integer value and store the result into one byte of the destination… | ||
| v_cvt_pknorm_i16_f16 | v_cvt_pknorm_i16_f16 | VOP3 | Convert from two half-precision float inputs to a packed signed normalized short and store the result into a vector register. | ||
| v_cvt_pknorm_i16_f32 | v_cvt_pknorm_i16_f32 | VOP2 | Convert from two single-precision float inputs to a packed signed normalized short and store the result into a vector register. | ||
| v_cvt_pknorm_u16_f16 | v_cvt_pknorm_u16_f16 | VOP3 | Convert from two half-precision float inputs to a packed unsigned normalized short and store the result into a vector register. | ||
| v_cvt_pknorm_u16_f32 | v_cvt_pknorm_u16_f32 | VOP2 | Convert from two single-precision float inputs to a packed unsigned normalized short and store the result into a vector register. | ||
| v_cvt_pkrtz_f16_f32 | v_cvt_pkrtz_f16_f32 | VOP2 | Convert two single-precision float inputs to a packed half-precision float value using round toward zero semantics (ignore the current rounding… | ||
| v_cvt_rpi_i32_f32 | v_cvt_rpi_i32_f32 | VOP1 | Convert from a single-precision float input to a signed 32-bit integer value using round to nearest integer semantics (ignore the default rounding… | ||
| v_cvt_scale_pk16_bf16_bf6 | v_cvt_scale_pk16_bf16_bf6 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scale_pk16_bf16_fp6 | v_cvt_scale_pk16_bf16_fp6 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scale_pk16_f16_bf6 | v_cvt_scale_pk16_f16_bf6 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scale_pk16_f16_fp6 | v_cvt_scale_pk16_f16_fp6 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scale_pk16_f32_bf6 | v_cvt_scale_pk16_f32_bf6 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scale_pk16_f32_fp6 | v_cvt_scale_pk16_f32_fp6 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scale_pk8_bf16_bf8 | v_cvt_scale_pk8_bf16_bf8 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scale_pk8_bf16_fp4 | v_cvt_scale_pk8_bf16_fp4 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scale_pk8_bf16_fp8 | v_cvt_scale_pk8_bf16_fp8 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_scale_pk8_f16_bf8 | v_cvt_scale_pk8_f16_bf8 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗