v_cmpx_t_f64 GPU Native ISA AMD Vector

Comparison

v_cmpx_t_f64

Set the per-lane condition code to 1. Store the result into the EXEC mask.

Also written as v_cmpx_tru_f64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 3.5)
0111110
31:25
10101111
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 175 in OP rebuilds 0x7D5E0000, an identifier AMD lists for this encoding. The same in AMD RDNA 3.

Format VOPC
Width 32 bits
Opcode 175
Identifier 0x7D5E0000

Operands

  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 64-bit double-precision floating point value. (OPR_SRC, FMT_NUM_F64)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOPC encoding (AMD RDNA 3.5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Example

v_cmpx_t_f64 -1, v[2:3]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources