v_cmpx_o_f16 GPU Native ISA AMD Vector

Comparison

v_cmpx_o_f16

Set the per-lane condition code to 1 iff the first input is orderable to the second input.

Encoding

Binary Layout (AMD CDNA 5)
0111110
31:25
10000111
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 135 in OP rebuilds 0x7D0E0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 55), AMD CDNA 3 (opcode 55), AMD CDNA 2 (opcode 55), AMD CDNA 1 (opcode 55), AMD RDNA 2 (opcode 223), AMD RDNA 1 (opcode 223). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format VOPC
Width 32 bits
Opcode 135
Identifier 0x7D0E0000

Operands

  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. (OPR_SRC, FMT_NUM_F16)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16-bit half-precision floating point value. (OPR_VGPR, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOPC encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Description

Set the per-lane condition code to 1 iff the first input is orderable to the second input. Store the result into the EXEC mask and to VCC or a scalar register.

Semantics

EXEC.u64[laneId] = D0.u64[laneId] = (!isNAN(64'F(S0.f16)) && !isNAN(64'F(S1.f16))); // D0 = VCC in VOPC encoding.

Example

v_cmpx_o_f16 -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources