v_cmpx_t_i32 GPU Native ISA AMD Vector

Comparison

v_cmpx_t_i32

Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register.

Also written as v_cmpx_tru_i32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
0111110
31:25
11010111
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 215 in OP rebuilds 0x7DAE0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (opcode 199), AMD RDNA 3 (opcode 199), AMD RDNA 2 (opcode 151), AMD RDNA 1 (opcode 151). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOPC
Width 32 bits
Opcode 215
Identifier 0x7DAE0000

Operands

  • vcc
    Written. Written in the assembly; this encoding has no field for it. N/A Data format: N/A (OPR_VCC, FMT_NUM_M64)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_I32)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOPC encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Semantics

EXEC.u64[laneId] = D0.u64[laneId] = 1'1U; // D0 = VCC in VOPC encoding.

Example

v_cmpx_t_i32 -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources