AMDGPU / GFX Instructions GPU Native ISA AMD
1960 instructions - showing 100 per page, page 19 of 20 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| v_pk_maximum3_f16 | v_pk_maximum3_f16 | VOP3P | Select the component-wise IEEE maximum() of three half-precision float inputs and store the result into a vector register. | ||
| v_pk_maximum_f16 | v_pk_maximum_f16 | VOP3P | gfx1100 | Select the component-wise IEEE maximum() of two packed half-precision float inputs and store the selected values into a vector register. | |
| v_pk_min3_i16 | v_pk_min3_i16 | VOP3P | AMDGPU VOP3P vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_pk_min3_num_f16 | v_pk_min3_num_f16 | VOP3P | AMDGPU VOP3P vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_pk_min3_u16 | v_pk_min3_u16 | VOP3P | AMDGPU VOP3P vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_pk_min_f16 | v_pk_min_f16 | VOP3P | gfx1100 | Select the component-wise minimum of two packed half-precision float inputs and store the result into a vector register. | |
| v_pk_min_i16 | v_pk_min_i16 | VOP3P | gfx1100 | Select the component-wise minimum of two packed signed 16-bit integer inputs and store the selected values into a vector register. | |
| v_pk_min_num_bf16 | v_pk_min_num_bf16 | VOP3P | AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_pk_min_num_f16 | v_pk_min_num_f16 | VOP3P | Select the component-wise IEEE minimumNumber() of two packed half-precision float inputs and store the selected values into a vector register. | ||
| v_pk_min_num_f64 | v_pk_min_num_f64 | VOP3P | AMDGPU VOP3P vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_pk_min_u16 | v_pk_min_u16 | VOP3P | gfx1100 | Select the component-wise minimum of two packed unsigned 16-bit integer inputs and store the selected values into a vector register. | |
| v_pk_minimum3_f16 | v_pk_minimum3_f16 | VOP3P | Select the component-wise IEEE minimum() of three half-precision float inputs and store the result into a vector register. | ||
| v_pk_minimum_f16 | v_pk_minimum_f16 | VOP3P | gfx1100 | Select the component-wise IEEE minimum() of two packed half-precision float inputs and store the selected values into a vector register. | |
| v_pk_mov_b32 | v_pk_mov_b32 | VOP3P | Move data from two vector inputs into two vector registers. | ||
| v_pk_mul_bf16 | v_pk_mul_bf16 | VOP3P | AMDGPU VOP3P vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_pk_mul_f16 | v_pk_mul_f16 | VOP3P | gfx1100 | Multiply two packed half-precision float inputs component-wise and store the result into a vector register. | |
| v_pk_mul_f32 | v_pk_mul_f32 | VOP3P | Multiply two packed single-precision float inputs component-wise and store the result into a vector register. | ||
| v_pk_mul_f64 | v_pk_mul_f64 | VOP3P | AMDGPU VOP3P vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_pk_mul_lo_u16 | v_pk_mul_lo_u16 | VOP3P | gfx1100 | Multiply two packed unsigned 16-bit integer inputs component-wise and store the low bits of each resulting component into a vector register. | |
| v_pk_sub_i16 | v_pk_sub_i16 | VOP3P | gfx1100 | Subtract the second packed signed 16-bit integer input from the first input component-wise and store the result into a vector register. | |
| v_pk_sub_nc_u64 | v_pk_sub_nc_u64 | VOP3P | AMDGPU VOP3P vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_pk_sub_u16 | v_pk_sub_u16 | VOP3P | gfx1100 | Subtract the second packed unsigned 16-bit integer input from the first input component-wise and store the result into a vector register. | |
| v_prng_b32 | v_prng_b32 | VOP1 | Generate a pseudorandom number using an LFSR (linear feedback shift register) seeded with the vector input, then store the result into a vector… | ||
| v_qsad_pk_u16_u8 | v_qsad_pk_u16_u8 | VOP3 | gfx1100 | Perform the V_SAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third… | |
| v_rcp_bf16 | v_rcp_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_rcp_f16 | v_rcp_f16 | VOP1 | Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a vector register. | ||
| v_rcp_f32 | v_rcp_f32 | VOP1 | gfx1100 | Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a vector register. | |
| v_rcp_f64 | v_rcp_f64 | VOP1 | gfx1100 | Calculate the reciprocal of the double-precision float input using IEEE rules and store the result into a vector register. | |
| v_rcp_iflag_f32 | v_rcp_iflag_f32 | VOP1 | gfx1100 | Calculate the reciprocal of the vector float input in a manner suitable for integer division and store the result into a vector register. | |
| v_readfirstlane_b32 | v_readfirstlane_b32 SDST, S0 | VOP1 | gfx942, gfx1100 | Vector ALU | Read the value of a VGPR from the first active lane into a scalar register. |
| v_readlane_b32 | v_readlane_b32 | VOP2 | gfx1100 | Read the scalar value in the specified lane of the first input where the lane select is in the second input. Store the result into a scalar register. | |
| v_rndne_f16 | v_rndne_f16 | VOP1 | gfx1100 | Round the half-precision float input to the nearest even integer and store the result in floating point format into a vector register. | |
| v_rndne_f32 | v_rndne_f32 | VOP1 | gfx1100 | Round the single-precision float input to the nearest even integer and store the result in floating point format into a vector register. | |
| v_rndne_f64 | v_rndne_f64 | VOP1 | gfx1100 | Round the double-precision float input to the nearest even integer and store the result in floating point format into a vector register. | |
| v_rsq_bf16 | v_rsq_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_rsq_f16 | v_rsq_f16 | VOP1 | Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a vector register. | ||
| v_rsq_f32 | v_rsq_f32 VDST, S0 | VOP1 | gfx942, gfx1100 | Vector ALU | Per-lane fast approximate reciprocal square root. |
| v_rsq_f64 | v_rsq_f64 | VOP1 | gfx1100 | Calculate the reciprocal of the square root of the double-precision float input using IEEE rules and store the result into a vector register. | |
| v_s_exp_f16 | v_s_exp_f16 | VOP3P | Calculate 2 raised to the power of the half-precision float input and store the result into a scalar register. | ||
| v_s_exp_f32 | v_s_exp_f32 | VOP3P | Calculate 2 raised to the power of the single-precision float input and store the result into a scalar register. | ||
| v_s_log_f16 | v_s_log_f16 | VOP3P | Calculate the base 2 logarithm of the half-precision float input and store the result into a scalar register. | ||
| v_s_log_f32 | v_s_log_f32 | VOP3P | Calculate the base 2 logarithm of the single-precision float input and store the result into a scalar register. | ||
| v_s_rcp_f16 | v_s_rcp_f16 | VOP3P | Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a scalar register. | ||
| v_s_rcp_f32 | v_s_rcp_f32 | VOP3P | Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a scalar register. | ||
| v_s_rsq_f16 | v_s_rsq_f16 | VOP3P | Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a scalar register. | ||
| v_s_rsq_f32 | v_s_rsq_f32 | VOP3P | Calculate the reciprocal of the square root of the single-precision float input using IEEE rules and store the result into a scalar register. | ||
| v_s_sqrt_f16 | v_s_sqrt_f16 | VOP3P | Calculate the square root of the half-precision float input using IEEE rules and store the result into a scalar register. | ||
| v_s_sqrt_f32 | v_s_sqrt_f32 | VOP3P | Calculate the square root of the single-precision float input using IEEE rules and store the result into a scalar register. | ||
| v_sad_hi_u8 | v_sad_hi_u8 | VOP3 | gfx1100 | Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an… | |
| v_sad_u16 | v_sad_u16 | VOP3 | gfx1100 | Calculate the sum of absolute differences of elements in two packed 2-component unsigned 16-bit integer inputs, add an unsigned 32-bit integer value… | |
| v_sad_u32 | v_sad_u32 | VOP3 | gfx1100 | Calculate the absolute difference of two unsigned 32-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the… | |
| v_sad_u8 | v_sad_u8 | VOP3 | gfx1100 | Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, add an unsigned 32-bit integer value… | |
| v_sat_pk4_i4_i8 | v_sat_pk4_i4_i8 | VOP1 | AMDGPU VOP1 vector instruction operating on i8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_sat_pk4_u4_u8 | v_sat_pk4_u4_u8 | VOP1 | AMDGPU VOP1 vector instruction operating on u8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_sat_pk_u8_i16 | v_sat_pk_u8_i16 | VOP1 | gfx1100 | Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value… | |
| v_screen_partition_4se_b32 | v_screen_partition_4se_b32 | VOP1 | 4SE version of LUT instruction for screen partitioning/filtering. | ||
| v_sin_bf16 | v_sin_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_sin_f16 | v_sin_f16 | VOP1 | gfx1100 | Calculate the trigonometric sine of a half-precision float value using IEEE rules and store the result into a vector register. | |
| v_sin_f32 | v_sin_f32 VDST, S0 | VOP1 | gfx942, gfx1100 | Vector ALU | Per-lane fast approximate sine. |
| v_smfmac_f32_16x16x128_bf8_bf8 | v_smfmac_f32_16x16x128_bf8_bf8 | VOP3P | Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored… | ||
| v_smfmac_f32_16x16x128_bf8_fp8 | v_smfmac_f32_16x16x128_bf8_fp8 | VOP3P | Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored… | ||
| v_smfmac_f32_16x16x128_fp8_bf8 | v_smfmac_f32_16x16x128_fp8_bf8 | VOP3P | Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored… | ||
| v_smfmac_f32_16x16x128_fp8_fp8 | v_smfmac_f32_16x16x128_fp8_fp8 | VOP3P | Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored… | ||
| v_smfmac_f32_16x16x128bf8bf8 | v_smfmac_f32_16x16x128bf8bf8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x128bf8fp8 | v_smfmac_f32_16x16x128bf8fp8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x128fp8bf8 | v_smfmac_f32_16x16x128fp8bf8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x128fp8fp8 | v_smfmac_f32_16x16x128fp8fp8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x32_bf16 | v_smfmac_f32_16x16x32_bf16 | VOP3P | Multiply the 16x32 sparse matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in… | ||
| v_smfmac_f32_16x16x32_f16 | v_smfmac_f32_16x16x32_f16 | VOP3P | Multiply the 16x32 sparse matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in… | ||
| v_smfmac_f32_16x16x32bf16 | v_smfmac_f32_16x16x32bf16 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x32f16 | v_smfmac_f32_16x16x32f16 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x64_bf16 | v_smfmac_f32_16x16x64_bf16 | VOP3P | Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in… | ||
| v_smfmac_f32_16x16x64_bf8_bf8 | v_smfmac_f32_16x16x64_bf8_bf8 | VOP3P | Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in… | ||
| v_smfmac_f32_16x16x64_bf8_fp8 | v_smfmac_f32_16x16x64_bf8_fp8 | VOP3P | Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in… | ||
| v_smfmac_f32_16x16x64_f16 | v_smfmac_f32_16x16x64_f16 | VOP3P | Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in… | ||
| v_smfmac_f32_16x16x64_fp8_bf8 | v_smfmac_f32_16x16x64_fp8_bf8 | VOP3P | Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in… | ||
| v_smfmac_f32_16x16x64_fp8_fp8 | v_smfmac_f32_16x16x64_fp8_fp8 | VOP3P | Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in… | ||
| v_smfmac_f32_16x16x64bf16 | v_smfmac_f32_16x16x64bf16 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x64bf8bf8 | v_smfmac_f32_16x16x64bf8bf8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x64bf8fp8 | v_smfmac_f32_16x16x64bf8fp8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x64f16 | v_smfmac_f32_16x16x64f16 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x64fp8bf8 | v_smfmac_f32_16x16x64fp8bf8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_16x16x64fp8fp8 | v_smfmac_f32_16x16x64fp8fp8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x16_bf16 | v_smfmac_f32_32x32x16_bf16 | VOP3P | Multiply the 32x16 sparse matrix in the first input by the 16x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x16_f16 | v_smfmac_f32_32x32x16_f16 | VOP3P | Multiply the 32x16 sparse matrix in the first input by the 16x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x16bf16 | v_smfmac_f32_32x32x16bf16 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x16f16 | v_smfmac_f32_32x32x16f16 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x32_bf16 | v_smfmac_f32_32x32x32_bf16 | VOP3P | Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x32_bf8_bf8 | v_smfmac_f32_32x32x32_bf8_bf8 | VOP3P | Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x32_bf8_fp8 | v_smfmac_f32_32x32x32_bf8_fp8 | VOP3P | Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x32_f16 | v_smfmac_f32_32x32x32_f16 | VOP3P | Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x32_fp8_bf8 | v_smfmac_f32_32x32x32_fp8_bf8 | VOP3P | Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x32_fp8_fp8 | v_smfmac_f32_32x32x32_fp8_fp8 | VOP3P | Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x32bf16 | v_smfmac_f32_32x32x32bf16 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x32bf8bf8 | v_smfmac_f32_32x32x32bf8bf8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x32bf8fp8 | v_smfmac_f32_32x32x32bf8fp8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x32f16 | v_smfmac_f32_32x32x32f16 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x32fp8bf8 | v_smfmac_f32_32x32x32fp8bf8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x32fp8fp8 | v_smfmac_f32_32x32x32fp8fp8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x64_bf8_bf8 | v_smfmac_f32_32x32x64_bf8_bf8 | VOP3P | Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗