v_dot8_i32_iu4 GPU Native ISA AMD Vector

Vector Packed Arithmetic

v_dot8_i32_iu4

Compute the dot product of two packed 8-D signed or unsigned 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer…

Also written as v_dot8_i32_i4. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OPSEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
11001100
31:24
00011000
23:16
CLAMP
15
OPSEL_HI[2]
14
OPSEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 24 in OP rebuilds 0x00000000CC180000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 4 (field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout).

Format VOP3P
Width 64 bits
Opcode 24
Identifier 0x00000000CC180000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Signed 32-bit integral data. (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed or unsigned 4-bit integral data; signedness is determined by opcode modifier. Packed 8-component value. (OPR_SRC, FMT_NUM_PK8_IU4)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed or unsigned 4-bit integral data; signedness is determined by opcode modifier. Packed 8-component value. (OPR_SRC, FMT_NUM_PK8_IU4)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 32-bit integral data. (OPR_SRC, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Compute the dot product of two packed 8-D signed or unsigned 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.

Example

v_dot8_i32_iu4 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources