v_mfma_f32_16x16x16_bf16 GPU Native ISA AMD Matrix
Vector Packed Arithmetic
Multiply the 16x16 matrix in the first input by the 16x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…
Also written as
v_mfma_f32_16x16x16bf16, v_mfma_f32_16x16x16bf16_1k.
AMD's machine-readable ISA specification lists these names for the same instruction.
Encoding
The VOP3P_MFMA layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 97 in OP rebuilds 0x00000000D3E10000, an identifier AMD lists for this encoding. The same in AMD CDNA 3.
Operands
-
VDST
Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_PK4_F32) -
SRC0
Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_PK4_BF16) -
SRC1
Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_PK4_BF16) -
SRC2
Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR_OR_CONST, FMT_NUM_PK4_F32)
In AMD's order, as its machine-readable ISA specification lists them for the VOP3P_MFMA encoding (AMD CDNA 4).
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx942 | ✅ Supported |
This instruction performs 4 passes.
Related
More in Vector Packed Arithmetic
Reference
Description
Semantics
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 280. - AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.