v_dot4_f32_fp8_bf8 GPU Native ISA AMD Vector

Vector Packed Arithmetic

v_dot4_f32_fp8_bf8

Compute the dot product of a packed 4-D FP8 float input and a packed 4-D BF8 float input in the single-precision float domain, add a single-precision…

Encoding

Binary Layout (AMD RDNA 4)
NEG
63:61
OPSEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
11001100
31:24
unassigned
23
0100100
22:16
CLAMP
15
OPSEL_HI[2]
14
OPSEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 36 in OP rebuilds 0x00000000CC240000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format VOP3P
Width 64 bits
Opcode 36
Identifier 0x00000000CC240000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Packed 4-component value. (OPR_SRC, FMT_NUM_PK4_FP8)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Packed 4-component value. (OPR_SRC, FMT_NUM_PK4_BF8)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD RDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Compute the dot product of a packed 4-D FP8 float input and a packed 4-D BF8 float input in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register.

Example

v_dot4_f32_fp8_bf8 v0, v1, v2, 1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1170_asm_vop3p.s). Not from an AMD document, and not authored here.

Sources