v_mfma_f32_16x16x8_xf32 GPU Native ISA AMD Matrix

Vector Packed Arithmetic

v_mfma_f32_16x16x8_xf32

Multiply the 16x8 matrix in the first input by the 8x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…

Also written as v_mfma_f32_16x16x8xf32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 3)
BLGP
63:61
ACC
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
0111110
22:16
ACC_CD
15
ABID
14:11
CBSZ
10:8
VDST
7:0
 

The VOP3P_MFMA layout from AMD's machine-readable ISA specification (AMD CDNA 3). Opcode 62 in OP rebuilds 0x00000000D3BE0000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP3P
Width 64 bits
Opcode 62
Identifier 0x00000000D3BE0000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_PK4_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_PK2_F32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_PK2_F32)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR_OR_CONST, FMT_NUM_PK4_F32)

In AMD's order, as its machine-readable ISA specification lists them for the VOP3P_MFMA encoding (AMD CDNA 3).

GFX Target Compatibility

TargetSupport
gfx942✅ Supported

This instruction performs 4 passes.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply the 16x8 matrix in the first input by the 8x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

Semantics

D = A (16x8) * B (8x16) + C (16x16) Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher performance. Matrices A and B are single-precision float format. Matrices C and D are single-precision float format. XF32 is a FP32 operation with FP32 inputs and outputs but implemented at reduced intermediate precision where mantissa is truncated to 10 bits (not including leading 1 for non-zero values) and results are accumulated into FP32 value with 23 bit mantissa.

Sources