v_mfma_f32_16x16x8_xf32 GPU Native ISA AMD Matrix

V MFMA F32 16X16X8 XF32 Vector Packed Arithmetic

v_mfma_f32_16x16x8_xf32

Multiply the 16x8 matrix in the first input by the 8x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3P) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3P
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx942✅ Supported

This instruction performs 4 passes.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply the 16x8 matrix in the first input by the 8x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

Semantics

D = A (16x8) * B (8x16) + C (16x16) Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher performance. Matrices A and B are single-precision float format. Matrices C and D are single-precision float format. XF32 is a FP32 operation with FP32 inputs and outputs but implemented at reduced intermediate precision where mantissa is truncated to 10 bits (not including leading 1 for non-zero values) and results are accumulated into FP32 value with 23 bit mantissa.

Sources