v_mfma_f32_32x32x2_f32 GPU Native ISA AMD Matrix

Vector Packed Arithmetic

v_mfma_f32_32x32x2_f32

Multiply the 32x2 matrix in the first input by the 2x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…

Also written as v_mfma_f32_32x32x2f32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
BLGP
63:61
ACC
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
1000100
22:16
ACC_CD
15
ABID
14:11
CBSZ
10:8
VDST
7:0
 

The VOP3P_MFMA layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 68 in OP rebuilds 0x00000000D3C40000, an identifier AMD lists for this encoding. The same in AMD CDNA 3.

Format VOP3P
Width 64 bits
Opcode 68
Identifier 0x00000000D3C40000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_PK16_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_F32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_F32)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR_OR_CONST, FMT_NUM_PK16_F32)

In AMD's order, as its machine-readable ISA specification lists them for the VOP3P_MFMA encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

This instruction performs 16 passes.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply the 32x2 matrix in the first input by the 2x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

Semantics

D = A (32x2) * B (2x32) + C (32x32) Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher performance. Matrices A and B are single-precision float format. Matrices C and D are single-precision float format.

Sources