v_mfma_f32_32x32x4_xf32 GPU Native ISA AMD Matrix
V MFMA F32 32X32X4 XF32 Vector Packed Arithmetic
v_mfma_f32_32x32x4_xf32
Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3P)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx942 | ✅ Supported |
This instruction performs 8 passes.
Related
More in Vector Packed Arithmetic
Reference
AMDGPU / GFX ISA
Description
Multiply the 32x4 matrix in the first input by the 4x32 matrix in the second input and add the 32x32 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.
Semantics
D = A (32x4) * B (4x32) + C (32x32)
Each operand contains a single matrix whose elements are distributed across all lanes of the wave. A single
matrix multiply is computed and the row-column dot products are distributed across the vector ALU for higher
performance.
Matrices A and B are single-precision float format. Matrices C and D are single-precision float format.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 272.