v_mad_mix_f32 GPU Native ISA AMD Vector

Vector Packed Arithmetic

v_mad_mix_f32

Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OP_SEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
0100000
22:16
CLAMP
15
OP_SEL_HI[2]
14
OP_SEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 32 in OP rebuilds 0x00000000D3A00000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP3P
Width 64 bits
Opcode 32
Identifier 0x00000000D3A00000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_B32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_B32)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values. Store the result into a vector register.

Semantics

Size and location of the three inputs are controlled by { OPSEL_HI[i], OPSEL[i] }: 0=src[31:0], 1=src[31:0], 2=src[15:0], 3=src[31:16]. For MIX opcodes the NEG_HI instruction field acts as an absolute-value modifier for the three inputs. declare in : 32'F[3]; declare S : 32'B[3]; for i in 0 : 2 do if !OPSEL_HI.u3[i] then in[i] = S[i].f32 elsif OPSEL.u3[i] then in[i] = f16_to_f32(S[i][31 : 16].f16) else in[i] = f16_to_f32(S[i][15 : 0].f16) endif endfor; D0[31 : 0].f32 = in[0] * in[1] + in[2]

Example

v_mad_mix_f32 v5, 0, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_vop3p.s). Not from an AMD document, and not authored here.

Sources