v_dot8_i32_i4 GPU Native ISA AMD Vector

Vector Packed Arithmetic

v_dot8_i32_i4

Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the…

Also written as v_dot8_i32_iu4. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OP_SEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
0101010
22:16
CLAMP
15
OP_SEL_HI[2]
14
OP_SEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 42 in OP rebuilds 0x00000000D3AA0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 24, field layout). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP3P
Width 64 bits
Opcode 42
Identifier 0x00000000D3AA0000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_PK8_I4)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_PK8_I4)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register.

Semantics

tmp = S2.i32; tmp += i4_to_i32(S0[3 : 0].i4) * i4_to_i32(S1[3 : 0].i4); tmp += i4_to_i32(S0[7 : 4].i4) * i4_to_i32(S1[7 : 4].i4); tmp += i4_to_i32(S0[11 : 8].i4) * i4_to_i32(S1[11 : 8].i4); tmp += i4_to_i32(S0[15 : 12].i4) * i4_to_i32(S1[15 : 12].i4); tmp += i4_to_i32(S0[19 : 16].i4) * i4_to_i32(S1[19 : 16].i4); tmp += i4_to_i32(S0[23 : 20].i4) * i4_to_i32(S1[23 : 20].i4); tmp += i4_to_i32(S0[27 : 24].i4) * i4_to_i32(S1[27 : 24].i4); tmp += i4_to_i32(S0[31 : 28].i4) * i4_to_i32(S1[31 : 28].i4); D0.i32 = tmp

Example

v_dot8_i32_i4 v0, v1, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (dl-insts.s). Not from an AMD document, and not authored here.

Sources