v_dot2_u32_u16 GPU Native ISA AMD Vector
Vector Packed Arithmetic
Compute the dot product of two packed 2-D unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value…
Encoding
The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 39 in OP rebuilds 0x00000000D3A70000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 21, field layout). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.
Operands
-
VDST
Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_U32) -
SRC0
Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_PK2_U16) -
SRC1
Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_PK2_U16) -
SRC2
Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_U32)
In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 4).
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related PTX Concepts
Related
More in Vector Packed Arithmetic
Reference
Description
Semantics
Example
v_dot2_u32_u16 v0, v1, v2, v3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (dl-insts.s). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 269. - AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.
- LLVM MC assembler tests for AMDGPU ↗ - LLVM Project