v_mad_mixhi_f16 GPU Native ISA AMD Vector

V MAD MIXHI F16 Vector Packed Arithmetic

v_mad_mixhi_f16

Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3P) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3P
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two inputs and add a third input where the inputs are a mix of half-precision float and single- precision float values. Convert the result to a half-precision float. Store the result into the high bits of a vector register.

Semantics

Size and location of the three inputs are controlled by { OPSEL_HI[i], OPSEL[i] }: 0=src[31:0], 1=src[31:0], 2=src[15:0], 3=src[31:16]. For MIX opcodes the NEG_HI instruction field acts as an absolute-value modifier for the three inputs. declare in : 32'F[3]; declare S : 32'B[3]; for i in 0 : 2 do if !OPSEL_HI.u3[i] then in[i] = S[i].f32 elsif OPSEL.u3[i] then in[i] = f16_to_f32(S[i][31 : 16].f16) else in[i] = f16_to_f32(S[i][15 : 0].f16) endif endfor; D0[31 : 16].f16 = f32_to_f16(in[0] * in[1] + in[2])

Sources