AMDGPU / GFX Instructions GPU Native ISA AMD
1960 instructions - showing 60 per page, page 20 of 20 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| v_smfmac_f32_32x32x64_bf8_fp8 | v_smfmac_f32_32x32x64_bf8_fp8 | VOP3P | Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x64_fp8_bf8 | v_smfmac_f32_32x32x64_fp8_bf8 | VOP3P | Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x64_fp8_fp8 | v_smfmac_f32_32x32x64_fp8_fp8 | VOP3P | Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_f32_32x32x64bf8bf8 | v_smfmac_f32_32x32x64bf8bf8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x64bf8fp8 | v_smfmac_f32_32x32x64bf8fp8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x64fp8bf8 | v_smfmac_f32_32x32x64fp8bf8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_f32_32x32x64fp8fp8 | v_smfmac_f32_32x32x64fp8fp8 | VOP3P | AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_i32_16x16x128_i8 | v_smfmac_i32_16x16x128_i8 | VOP3P | Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored… | ||
| v_smfmac_i32_16x16x128i8 | v_smfmac_i32_16x16x128i8 | VOP3P | AMDGPU VOP3P matrix instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_i32_16x16x64_i8 | v_smfmac_i32_16x16x64_i8 | VOP3P | Multiply the 16x64 sparse matrix in the first input by the 64x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in… | ||
| v_smfmac_i32_16x16x64i8 | v_smfmac_i32_16x16x64i8 | VOP3P | AMDGPU VOP3P matrix instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_i32_32x32x32_i8 | v_smfmac_i32_32x32x32_i8 | VOP3P | Multiply the 32x32 sparse matrix in the first input by the 32x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_i32_32x32x32i8 | v_smfmac_i32_32x32x32i8 | VOP3P | AMDGPU VOP3P matrix instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_smfmac_i32_32x32x64_i8 | v_smfmac_i32_32x32x64_i8 | VOP3P | Multiply the 32x64 sparse matrix in the first input by the 64x32 matrix in the second input and accumulate the result into the 32x32 matrix stored in… | ||
| v_smfmac_i32_32x32x64i8 | v_smfmac_i32_32x32x64i8 | VOP3P | AMDGPU VOP3P matrix instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_sqrt_bf16 | v_sqrt_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_sqrt_f16 | v_sqrt_f16 | VOP1 | Calculate the square root of the half-precision float input using IEEE rules and store the result into a vector register. | ||
| v_sqrt_f32 | v_sqrt_f32 | VOP1 | gfx1100 | Calculate the square root of the single-precision float input using IEEE rules and store the result into a vector register. | |
| v_sqrt_f64 | v_sqrt_f64 | VOP1 | gfx1100 | Calculate the square root of the double-precision float input using IEEE rules and store the result into a vector register. | |
| v_sub_co_u32 | v_sub_co_u32 | VOP2 | gfx1100 | Subtract the second unsigned 32-bit integer input from the first input, store the result into a vector register and store the carry-out mask into a… | |
| v_sub_f16 | v_sub_f16 | VOP2 | gfx1100 | Subtract the second floating point input from the first input and store the result into a vector register. | |
| v_sub_f32 | v_sub_f32 VDST, S0, S1 | VOP2 | gfx942, gfx1100 | Vector ALU | Per-lane single-precision floating-point subtract. |
| v_sub_i16 | v_sub_i16 | VOP3 | Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. | ||
| v_sub_i32 | v_sub_i32 | VOP2 | Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. | ||
| v_sub_nc_i16 | v_sub_nc_i16 | VOP3 | gfx1100 | Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. | |
| v_sub_nc_i32 | v_sub_nc_i32 | VOP3 | gfx1100 | Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. | |
| v_sub_nc_u16 | v_sub_nc_u16 | VOP3 | gfx1100 | Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. | |
| v_sub_nc_u64 | v_sub_nc_u64 | VOP2 | AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_sub_u16 | v_sub_u16 | VOP2 | Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. | ||
| v_sub_u32 | v_sub_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. | ||
| v_subb_co_u32 | v_subb_co_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input, subtract a bit from the carry-in mask, store the result into a vector… | ||
| v_subb_u32 | v_subb_u32 | VOP2 | AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_subbrev_co_u32 | v_subbrev_co_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector… | ||
| v_subbrev_u32 | v_subbrev_u32 | VOP2 | AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_subrev_co_u32 | v_subrev_co_u32 | VOP2 | gfx1100 | Subtract the first unsigned 32-bit integer input from the second input, store the result into a vector register and store the carry-out mask into a… | |
| v_subrev_f16 | v_subrev_f16 | VOP2 | gfx1100 | Subtract the first floating point input from the second input and store the result into a vector register. | |
| v_subrev_f32 | v_subrev_f32 | VOP2 | gfx1100 | Subtract the first floating point input from the second input and store the result into a vector register. | |
| v_subrev_i32 | v_subrev_i32 | VOP2 | AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_subrev_u16 | v_subrev_u16 | VOP2 | Subtract the first unsigned 16-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support. | ||
| v_subrev_u32 | v_subrev_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support. | ||
| v_swap_b16 | v_swap_b16 | VOP1 | gfx1100 | Swap the values in two vector registers. | |
| v_swap_b32 | v_swap_b32 | VOP1 | gfx1100 | Swap the values in two vector registers. | |
| v_swaprel_b32 | v_swaprel_b32 | VOP1 | gfx1100 | Swap the values in two relatively-indexed vector registers. | |
| v_tanh_bf16 | v_tanh_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_tanh_f16 | v_tanh_f16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_tanh_f32 | v_tanh_f32 | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_trig_preop_f64 | v_trig_preop_f64 | VOP3 | gfx1100 | Look up a 53-bit segment of 2/PI using an integer segment select in the second input. | |
| v_trunc_f16 | v_trunc_f16 | VOP1 | gfx1100 | Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a… | |
| v_trunc_f32 | v_trunc_f32 | VOP1 | gfx1100 | Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a… | |
| v_trunc_f64 | v_trunc_f64 | VOP1 | gfx1100 | Compute the integer part of a double-precision float input using round toward zero semantics and store the result in floating point format into a… | |
| v_wmma_ld_scale16_paired_b64 | v_wmma_ld_scale16_paired_b64 | VOP3P | AMDGPU VOP3P matrix instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_wmma_ld_scale_paired_b32 | v_wmma_ld_scale_paired_b32 | VOP3P | AMDGPU VOP3P matrix instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_writelane_b32 | v_writelane_b32 | VOP2 | gfx1100 | Write the scalar value in the first input into the specified lane of a vector register where the lane select is in the second input. | |
| v_xad_u32 | v_xad_u32 | VOP3 | gfx1100 | Calculate bitwise XOR of the first two vector inputs, then add the third vector input to the intermediate result, then store the final result into a… | |
| v_xnor_b32 | v_xnor_b32 | VOP2 | gfx1100 | Calculate bitwise XNOR on two vector inputs and store the result into a vector register. | |
| v_xor3_b32 | v_xor3_b32 | VOP3 | gfx1100 | Calculate the bitwise XOR of three vector inputs and store the result into a vector register. | |
| v_xor_b16 | v_xor_b16 | VOP3 | gfx1100 | Calculate bitwise XOR on two vector inputs and store the result into a vector register. | |
| v_xor_b16_fake16 | v_xor_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_xor_b16_t16 | v_xor_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_xor_b32 | v_xor_b32 | VOP2 | gfx1100 | Calculate bitwise XOR on two vector inputs and store the result into a vector register. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗