v_interp_p2_f32 GPU Native ISA AMD Vector

Vector Interpolation

v_interp_p2_f32

Given the J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in the destination vector register…

Also written as v_interp_p2_new_f32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VINTERP) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VINTERP

Operands

  • 1: VGPR
    Vector general-purpose register, one value per lane. Written v0 in the assembler example.
  • 2: VGPR
    Vector general-purpose register, one value per lane. Written -v1 in the assembler example.
  • 3: VGPR
    Vector general-purpose register, one value per lane. Written v2 in the assembler example.
  • 4: VGPR
    Vector general-purpose register, one value per lane. Written v3 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Interpolation

Reference

AMDGPU / GFX ISA

Description

Given the J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in the destination vector register, load parameter data from the local data share, compute the second part of parameter interpolation and store the final result into a vector register.

Example

v_interp_p2_f32 v0, -v1, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources