v_interp_p2_f32 GPU Native ISA AMD Vector
V INTERP P2 F32 Vector Interpolation
v_interp_p2_f32
Given the J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in the destination vector register…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VINTERP)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Vector Interpolation
Reference
AMDGPU / GFX ISA
Description
Given the J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in the destination vector register, load parameter data from the local data share, compute the second part of parameter interpolation and store the final result into a vector register.
Example
v_interp_p2_f32 v0, -v1, v2, v3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.
- LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project