v_interp_p10_f32 GPU Native ISA AMD Vector

Vector Interpolation

v_interp_p10_f32

Given the P10 parameter of an attribute, the I coordinate and the P0 parameter as single-precision float inputs, compute the first part of parameter…

Encoding

Binary Layout (AMD RDNA 4)
NEG
63:61
unassigned
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
11001101
31:24
unassigned
23:21
00000
20:16
CLAMP
15
OPSEL
14:11
WAIT_EXP
10:8
VDST
7:0
 

The ENC_VINTERP layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 0 in OP rebuilds 0x00000000CD000000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout).

Format VINTERP
Width 64 bits
Opcode 0
Identifier 0x00000000CD000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_SRC_VGPR, FMT_NUM_F32)
  • SRC1
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_SRC_VGPR, FMT_NUM_F32)
  • SRC2
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_SRC_VGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VINTERP encoding (AMD RDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Interpolation

Reference

AMDGPU / GFX ISA

Description

Given the P10 parameter of an attribute, the I coordinate and the P0 parameter as single-precision float inputs, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F32 to complete the operation.

Example

v_interp_p10_f32 v0, -v1, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources