scratch_store_dwordx3 GPU Native ISA AMD Vector
SCRATCH STORE DWORDX3 Scratch Memory
scratch_store_dwordx3
Store 96 bits of data from vector input registers into the scratch aperture.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SCRATCH)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Scratch Memory
Reference
AMDGPU / GFX ISA
Semantics
addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
MEM[addr].b32 = VDATA[31 : 0];
MEM[addr + 4U].b32 = VDATA[63 : 32];
MEM[addr + 8U].b32 = VDATA[95 : 64]
Example
scratch_store_dwordx3 v1, v[2:4], s3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 500. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project