scratch_store_block GPU Native ISA AMD Vector

Scratch Memory

scratch_store_block

Store a block of data to the scratch aperture.

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
unassigned
63
VSRC
62:55
TH
54:52
SCOPE
51:50
SVE
49
SCALE_OFFSET
48
unassigned
47:40
VDST
39:32
11101101
31:24
unassigned
23:22
01010100
21:14
unassigned
13:8
NV
7
SADDR
6:0
 

The ENC_VSCRATCH layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 84 in OP rebuilds 0x0000000000000000ED150000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 4 (field layout).

Format SCRATCH
Width 96 bits
Opcode 84
Identifier 0x0000000000000000ED150000

Operands

  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VSRC
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. Any scalar GPR operand including VCC and NULL. Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VSCRATCH encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scratch Memory

Reference

AMDGPU / GFX ISA

Example

scratch_store_block v1, v[2:33], s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_vflat.s). Not from an AMD document, and not authored here.

Sources