scratch_load_sbyte_d16_hi GPU Native ISA AMD Vector

Scratch Memory

scratch_load_sbyte_d16_hi

Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.

Also written as scratch_load_d16_hi_i8. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SCRATCH) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SCRATCH

Operands

  • VDST
    Written. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)
  • ADDR
    Read. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. N/A Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_FLAT_SCRATCH encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scratch Memory

Reference

AMDGPU / GFX ISA

Semantics

addr = CalcScratchAddr(ADDR.b32, SADDR.b32, OFFSET.b32); VDATA[31 : 16].i16 = 16'I(signext(MEM[addr].i8)); // VDATA[15:0] is preserved.

Example

scratch_load_sbyte_d16_hi v2, v4, s6

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (flat-scratch-gfx942.s). Not from an AMD document, and not authored here.

Sources