RISC-V Instructions

547 instructions - showing 100 per page, page 5 of 6 - click any row to view encoding, pseudocode, and full documentation.

RISC-V Unprivileged ISA Specification RISC-V Privileged Architecture Specification
By extension → 100 instructions
Mnemonic ⇅ Syntax Format ⇅ Extension ⇅ Summary
VLE16.V VLE16.V vd, (rs1), vm VL-Type V Loads a vector of 16-bit elements from memory.
VLE16FF.V VLE16FF.V vd, (rs1), vm VL-Type V Loads 16-bit elements with fault suppression.
VLE32.V VLE32.V vd, (rs1), vm V-Load V Loads a vector of 32-bit elements from memory into a vector register.
VLE32FF.V VLE32FF.V vd, (rs1), vm VL-Type V Loads 32-bit elements with fault suppression.
VLE64.V VLE64.V vd, (rs1), vm VL-Type V Loads a vector of 64-bit elements from memory.
VLE64FF.V VLE64FF.V vd, (rs1), vm VL-Type V Loads 64-bit elements with fault suppression.
VLE8.V VLE8.V vd, (rs1), vm VL-Type V Loads a vector of 8-bit elements from memory.
VLE8FF.V VLE8FF.V vd, (rs1), vm VL-Type V Loads 8-bit elements, suppressing faults on elements after the first. Sets VL to number of elements loaded. Critical for strings.
VLM.V VLM.V vd, (rs1) VL-Type V Loads a vector mask register from memory.
VLOXEI32.V VLOXEI32.V vd, (rs1), vs2, vm VL-Type V Loads elements using indices, ensuring order (useful for I/O buffers).
VLSE32.V VLSE32.V vd, (rs1), rs2, vm VL-Type V Loads elements from memory with a fixed stride.
VLSEG2E16.V VLSEG2E16.V vd, (rs1), vm VL-Type V Loads 2 fields (e.g., Complex Real/Imag) of 16-bit elements.
VLSEG3E8.V VLSEG3E8.V vd, (rs1), vm VL-Type V Loads 3 fields (e.g., RGB) of 8-bit elements into 3 vector registers.
VLSEG4E8.V VLSEG4E8.V vd, (rs1), vm VL-Type V Loads 4 fields (e.g., RGBA) of 8-bit elements into 4 vector registers.
VLUXEI32.V VLUXEI32.V vd, (rs1), vs2, vm VL-Type V Loads elements from memory using a vector of indices (Gather).
VMACC.VV VMACC.VV vd, vs1, vs2, vm OPIVV V Computes vd = vd + (vs1 * vs2). Essential for dot products.
VMADC.VIM VMADC.VIM vd, vs2, imm, v0 OPIVI V Add Immediate with Carry.
VMADC.VVM VMADC.VVM vd, vs2, vs1, v0 OPIVV V Adds two vectors and a carry-in, producing the carry-out to the destination mask.
VMAND.MM VMAND.MM vd, vs2, vs1 OPMVV V Performs bitwise AND on vector mask registers.
VMANDN.MM VMANDN.MM vd, vs2, vs1 OPMVV V Computes vd = vs1 & ~vs2 (mask operation).
VMAX.VV VMAX.VV vd, vs2, vs1, vm OPIVV V Computes the signed maximum of elements in two vectors.
VMAXU.VV VMAXU.VV vd, vs2, vs1, vm OPIVV V Computes the unsigned maximum of elements in two vectors.
VMERGE.VIM VMERGE.VIM vd, vs2, imm, v0 OPIVI V Merges immediate vs vector based on mask.
VMERGE.VVM VMERGE.VVM vd, vs2, vs1, v0 OPIVV V Merges two vectors based on the mask (if mask=0, pick vs2; if mask=1, pick vs1).
VMERGE.VXM VMERGE.VXM vd, vs2, rs1, v0 OPIVX V Merges integer scalar vs vector based on mask.
VMFEQ.VV VMFEQ.VV vd, vs2, vs1, vm OPFVV V Compares float vectors for equality, writing result to mask register.
VMFLE.VV VMFLE.VV vd, vs2, vs1, vm OPFVV V Compares float vectors (vs2 <= vs1), writing result to mask register.
VMFLT.VV VMFLT.VV vd, vs2, vs1, vm OPFVV V Compares float vectors (vs2 < vs1), writing result to mask register.
VMIN.VV VMIN.VV vd, vs2, vs1, vm OPIVV V Computes the signed minimum of elements in two vectors.
VMINU.VV VMINU.VV vd, vs2, vs1, vm OPIVV V Computes the unsigned minimum of elements in two vectors.
VMNAND.MM VMNAND.MM vd, vs2, vs1 OPMVV V Performs bitwise NAND on vector mask registers. Used to invert masks (NOT).
VMORN.MM VMORN.MM vd, vs2, vs1 OPMVV V Computes vd = vs1 | ~vs2 (mask operation).
VMSBC.VV VMSBC.VV vd, vs2, vs1 OPMVV V Writes a mask where bits are 1 before the first element in vs2 that is 1.
VMSBF.M VMSBF.M vd, vs2, vm OPMVV V Sets mask bits before the first set bit in the source mask.
VMSEQ.VI VMSEQ.VI vd, vs2, imm, vm OPIVI V Sets mask if element == imm.
VMSEQ.VV VMSEQ.VV vd, vs2, vs1, vm OPIVV V Sets destination mask bit if elements are equal.
VMSGE.VV VMSGE.VV vd, vs2, vs1, vm OPIVV V Sets mask if vs2 >= vs1.
VMSGEU.VV VMSGEU.VV vd, vs2, vs1, vm OPIVV V Sets mask if vs2 >= vs1 (Unsigned).
VMSGT.VV VMSGT.VV vd, vs2, vs1, vm OPIVV V Sets mask if vs2 > vs1.
VMSGTU.VV VMSGTU.VV vd, vs2, vs1, vm OPIVV V Sets mask if vs2 > vs1 (Unsigned).
VMSIF.M VMSIF.M vd, vs2, vm OPMVV V Sets mask bits up to and including the first set bit in the source.
VMSLE.VI VMSLE.VI vd, vs2, imm, vm OPIVI V Sets mask if element <= imm (Signed).
VMSLE.VV VMSLE.VV vd, vs2, vs1, vm OPIVV V Sets mask if vs2 <= vs1.
VMSLEU.VI VMSLEU.VI vd, vs2, imm, vm OPIVI V Sets mask if element <= imm (Unsigned).
VMSLEU.VV VMSLEU.VV vd, vs2, vs1, vm OPIVV V Sets mask if vs2 <= vs1 (Unsigned).
VMSLT.VI VMSLT.VI vd, vs2, imm, vm OPIVI V Sets mask if element < imm (Signed).
VMSLT.VV VMSLT.VV vd, vs2, vs1, vm OPIVV V Sets destination mask bit if vs2 < vs1 (signed).
VMSLTU.VI VMSLTU.VI vd, vs2, imm, vm OPIVI V Sets mask if element < imm (Unsigned).
VMSLTU.VV VMSLTU.VV vd, vs2, vs1, vm OPIVV V Sets destination mask bit if vs2 < vs1 (unsigned).
VMSNE.VI VMSNE.VI vd, vs2, imm, vm OPIVI V Sets mask if element != imm.
VMSOF.M VMSOF.M vd, vs2, vm OPMVV V Sets only the first set bit from the source mask.
VMUL.VV VMUL.VV vd, vs2, vs1, vm OPIVV V Multiplies elements of two vector registers.
VMULH.VV VMULH.VV vd, vs2, vs1, vm OPIVV V Multiplies signed integers and keeps the high N bits.
VMULHU.VV VMULHU.VV vd, vs2, vs1, vm OPIVV V Multiplies unsigned integers and keeps the high N bits.
VMV.S.X VMV.S.X vd, rs1 OPMVX V Copies an integer register to element 0 of a vector.
VMV.V.V VMV.V.V vd, vs1 OPIVV V Copies a vector register.
VMV.X.S VMV.X.S rd, vs2 OPMVX V Copies element 0 of a vector to an integer register.
VMV1R.V VMV1R.V vd, vs2 OPVI V Moves a single vector register to another, ignoring VL and VTYPE (used for spilling).
VMV2R.V VMV2R.V vd, vs2 OPVI V Moves 2 consecutive vector registers, ignoring VL and VTYPE.
VMV4R.V VMV4R.V vd, vs2 OPVI V Moves 4 consecutive vector registers, ignoring VL and VTYPE.
VMV8R.V VMV8R.V vd, vs2 OPVI V Moves 8 consecutive vector registers, ignoring VL and VTYPE.
VMXNOR.MM VMXNOR.MM vd, vs2, vs1 OPMVV V Computes vd = ~(vs1 ^ vs2) (mask operation).
VNCLIP.WV VNCLIP.WV vd, vs2, vs1, vm OPIVV V Shifts elements right, rounds, and clips (saturates) the result to the destination width. Critical for Quantization.
VNCLIPU.WI VNCLIPU.WI vd, vs2, imm, vm OPIVI V Shifts right (logical), rounds, and clips to unsigned destination. Used for pixel packing.
VNMSUB.VV VNMSUB.VV vd, vs1, vs2, vm OPIVV V Computes vd = -(vd - (vs1 * vs2)).
VNSRA.WI VNSRA.WI vd, vs2, imm, vm OPIVI V Shifts wide elements right (arithmetic) by immediate and narrows.
VNSRA.WX VNSRA.WX vd, vs2, rs1, vm OPIVX V Arithmetically shifts 2*N-bit elements right and narrows to N-bits.
VNSRL.WI VNSRL.WI vd, vs2, imm, vm OPIVI V Shifts wide elements right by immediate and narrows.
VNSRL.WX VNSRL.WX vd, vs2, rs1, vm OPIVX V Shifts 2*N-bit elements right and narrows the result to N-bits.
VOR.VI VOR.VI vd, vs2, imm, vm OPIVI V Bitwise OR with immediate.
VOR.VV VOR.VV vd, vs2, vs1, vm OPIVV V Performs bitwise OR on elements of two vectors.
VREDAND.VS VREDAND.VS vd, vs2, vs1, vm OPMVV V Reduces a vector to a scalar using bitwise AND.
VREDMAX.VS VREDMAX.VS vd, vs2, vs1, vm OPMVV V Reduces a vector to a scalar by finding the maximum signed element.
VREDMIN.VS VREDMIN.VS vd, vs2, vs1, vm OPMVV V Reduces a vector to a scalar by finding the minimum signed element.
VREDOR.VS VREDOR.VS vd, vs2, vs1, vm OPMVV V Reduces a vector to a scalar using bitwise OR.
VREDSUM.VS VREDSUM.VS vd, vs2, vs1, vm OPMVV V Reduces a vector to a scalar by summing all elements.
VREM.VV VREM.VV vd, vs2, vs1, vm OPIVV V Computes signed remainder.
VREMU.VV VREMU.VV vd, vs2, vs1, vm OPIVV V Computes unsigned remainder.
VREV8.V VREV8.V vd, vs2, vm OPIVV Zvbb Reverses the order of bytes within each element (Endian swap).
VRGATHER.VI VRGATHER.VI vd, vs2, imm, vm OPIVI V Gathers element at index 'imm' from vs2 (splat).
VRGATHER.VV VRGATHER.VV vd, vs2, vs1, vm OPIVV V Gathers elements from a vector register using indices from another vector register.
VROL.VV VROL.VV vd, vs2, vs1, vm OPIVV Zvbb Rotates bits in elements of vs2 left by amounts in vs1.
VROL.VX VROL.VX vd, vs2, rs1, vm OPIVX Zvbb Rotates bits in elements of vs2 left by scalar rs1.
VROR.VV VROR.VV vd, vs2, vs1, vm OPIVV Zvbb Rotates bits in elements of vs2 right by amounts in vs1.
VROR.VX VROR.VX vd, vs2, rs1, vm OPIVX Zvbb Rotates bits in elements of vs2 right by scalar rs1.
VRSUB.VI VRSUB.VI vd, vs2, imm, vm OPIVI V Computes vd = imm - vs2.
VRSUB.VX VRSUB.VX vd, vs2, rs1, vm OPIVX V Subtracts vector elements from a scalar value (scalar - vector).
VSADD.VV VSADD.VV vd, vs2, vs1, vm OPIVV V Adds elements with signed saturation (clips to Max/Min instead of wrapping).
VSADDU.VV VSADDU.VV vd, vs2, vs1, vm OPIVV V Adds unsigned integers with saturation (clips to max instead of wrapping).
VSBC.VVM VSBC.VVM vd, vs2, vs1, v0 OPIVV V Subtracts two vectors minus a borrow-in from the mask register.
VSE16.V VSE16.V vs3, (rs1), vm VS-Type V Stores a vector of 16-bit elements to memory.
VSE32.V VSE32.V vs3, (rs1), vm V-Store V Stores a vector of 32-bit elements from a vector register to memory.
VSE64.V VSE64.V vs3, (rs1), vm VS-Type V Stores a vector of 64-bit elements to memory.
VSE8.V VSE8.V vs3, (rs1), vm VS-Type V Stores a vector of 8-bit elements to memory.
VSETIVLI VSETIVLI rd, uimm, vtypei V-Type V Sets vector length (VL) and type (VTYPE) using a 5-bit immediate for the requested length.
VSETVL VSETVL rd, rs1, rs2 V-Type V Sets the vector length (VL) based on the application vector length (AVL) in rs1 and configuration in rs2.
VSETVLI VSETVLI rd, rs1, vtypei V-Type V Configures the vector length (vl) and vector type (vtype) based on application needs.
VSHA2CH.VV VSHA2CH.VV vd, vs2, vs1 OPIVV Zvknha Performs SHA-256 compression (high 128 bits).
VSHA2CL.VV VSHA2CL.VV vd, vs2, vs1 OPIVV Zvknha Performs SHA-256 compression (low 128 bits).
VSHA2MS.VV VSHA2MS.VV vd, vs2, vs1 OPIVV Zvknha Generates SHA-256 message schedule words.