RISC-V Instructions

547 instructions - showing 47 per page, page 6 of 6 - click any row to view encoding, pseudocode, and full documentation.

RISC-V Unprivileged ISA Specification RISC-V Privileged Architecture Specification
By extension → 47 instructions
Mnemonic ⇅ Syntax Format ⇅ Extension ⇅ Summary
VSLIDE1DOWN.VX VSLIDE1DOWN.VX vd, vs2, rs1, vm OPIVX V Moves elements down by 1, injecting scalar into top index.
VSLIDE1UP.VX VSLIDE1UP.VX vd, vs2, rs1, vm OPIVX V Moves elements up by 1, injecting scalar into index 0.
VSLIDEDOWN.VI VSLIDEDOWN.VI vd, vs2, imm, vm OPIVI V Moves elements down by immediate amount.
VSLIDEDOWN.VX VSLIDEDOWN.VX vd, vs2, rs1, vm OPIVX V Moves elements down by a scalar amount (vd[i] = vs2[i + rs1]).
VSLIDEUP.VI VSLIDEUP.VI vd, vs2, imm, vm OPIVI V Moves elements up by immediate amount.
VSLIDEUP.VX VSLIDEUP.VX vd, vs2, rs1, vm OPIVX V Moves elements up by a scalar amount (vd[i] = vs2[i - rs1]).
VSLL.VI VSLL.VI vd, vs2, imm, vm OPIVI V Shifts elements left by immediate.
VSLL.VV VSLL.VV vd, vs2, vs1, vm OPIVV V Shifts elements of vector vs2 left by amounts in vs1.
VSM.V VSM.V vs3, (rs1) VS-Type V Stores a vector mask register to memory.
VSMUL.VV VSMUL.VV vd, vs2, vs1, vm OPIVV V Performs signed saturating multiplication, keeping the high half of the product (Fixed-point support).
VSOXEI32.V VSOXEI32.V vs3, (rs1), vs2, vm VS-Type V Stores elements using indices, ensuring order.
VSRA.VI VSRA.VI vd, vs2, imm, vm OPIVI V Shifts elements right (arithmetic) by immediate.
VSRA.VV VSRA.VV vd, vs2, vs1, vm OPIVV V Shifts elements of vector vs2 right (arithmetic) by amounts in vs1.
VSRL.VI VSRL.VI vd, vs2, imm, vm OPIVI V Shifts elements right (logical) by immediate.
VSRL.VV VSRL.VV vd, vs2, vs1, vm OPIVV V Shifts elements of vector vs2 right (logical) by amounts in vs1.
VSSE32.V VSSE32.V vs3, (rs1), rs2, vm VS-Type V Stores elements to memory with a fixed stride.
VSSEG2E16.V VSSEG2E16.V vs3, (rs1), vm VS-Type V Stores 2 vector registers as interleaved 16-bit fields.
VSSEG3E8.V VSSEG3E8.V vs3, (rs1), vm VS-Type V Stores 3 vector registers (e.g., RGB) into memory as interleaved 8-bit fields.
VSSEG4E8.V VSSEG4E8.V vs3, (rs1), vm VS-Type V Stores 4 vector registers (e.g., RGBA) into memory as interleaved 8-bit fields.
VSSRA.VV VSSRA.VV vd, vs2, vs1, vm OPIVV V Shifts right with sign extension and rounding/saturation logic.
VSSRL.VV VSSRL.VV vd, vs2, vs1, vm OPIVV V Shifts right with zero extension and rounding/saturation logic.
VSSUB.VV VSSUB.VV vd, vs2, vs1, vm OPIVV V Subtracts elements with signed saturation.
VSSUBU.VV VSSUBU.VV vd, vs2, vs1, vm OPIVV V Subtracts unsigned integers with saturation (clips to 0 instead of wrapping).
VSUB.VV VSUB.VV vd, vs2, vs1, vm OPIVV V Subtracts elements of two vector registers.
VSUXEI32.V VSUXEI32.V vs3, (rs1), vs2, vm VS-Type V Stores elements to memory using a vector of indices (Scatter).
VWADD.VV VWADD.VV vd, vs2, vs1, vm OPIVV V Adds N-bit elements to produce 2*N-bit results (Widening).
VWADDU.VV VWADDU.VV vd, vs2, vs1, vm OPIVV V Adds unsigned N-bit elements to produce unsigned 2*N-bit results.
VWMACC.VV VWMACC.VV vd, vs1, vs2, vm OPIVV V Computes vd = vd + (vs1 * vs2) with widening (N*N -> 2N + 2N).
VWMACCSU.VV VWMACCSU.VV vd, vs1, vs2, vm OPIVV V vd = vd + (signed(vs1) * unsigned(vs2)).
VWMACCU.VV VWMACCU.VV vd, vs1, vs2, vm OPIVV V Computes vd = vd + (vs1 * vs2) widening unsigned.
VWMACCUS.VX VWMACCUS.VX vd, rs1, vs2, vm OPIVV V vd = vd + (unsigned(vs1) * signed(vs2)).
VWMUL.VV VWMUL.VV vd, vs2, vs1, vm OPIVV V Multiplies N-bit elements to produce 2*N-bit results.
VWREDSUM.VS VWREDSUM.VS vd, vs2, vs1, vm OPMVV V Sums N-bit elements into a 2*N-bit scalar accumulator (Signed).
VWREDSUMU.VS VWREDSUMU.VS vd, vs2, vs1, vm OPMVV V Sums N-bit elements into a 2*N-bit scalar accumulator (Unsigned).
VWSLL.VI VWSLL.VI vd, vs2, imm, vm OPIVI Zvbb Shifts elements left by immediate, widening the result.
VWSLL.VV VWSLL.VV vd, vs2, vs1, vm OPIVV Zvbb Shifts N-bit elements left to produce 2*N-bit results.
VWSLL.VX VWSLL.VX vd, vs2, rs1, vm OPIVX Zvbb Shifts elements left by scalar rs1, widening the result.
VWSUB.VV VWSUB.VV vd, vs2, vs1, vm OPIVV V Subtracts N-bit elements to produce 2*N-bit results.
VXOR.VI VXOR.VI vd, vs2, imm, vm OPIVI V Bitwise XOR with immediate.
VXOR.VV VXOR.VV vd, vs2, vs1, vm OPIVV V Performs bitwise XOR on elements of two vectors.
WFI WFI R-Type (System) Privileged Provides a hint to the implementation that the current hart can be stalled until an interrupt occurs.
WRS.NTO WRS.NTO I-Type Zawrs Stalls the hart until a reservation set is invalid or a short timeout expires. Used for efficient polling/spinlocks.
WRS.STO WRS.STO I-Type Zawrs Stalls the hart until a reservation set is invalid or a very short implementation-defined timeout expires.
XNOR XNOR rd, rs1, rs2 R-Type Zbb Performs bitwise exclusive-NOR (rs1 ^ ~rs2).
XOR XOR rd, rs1, rs2 R-Type RV32I Performs a bitwise logical Exclusive-OR operation.
XORI XORI rd, rs1, imm I-Type RV32I Performs a bitwise logical Exclusive-OR with a sign-extended immediate.
ZEXT.H ZEXT.H rd, rs1 I-Type Zbb Zero-extends the lowest halfword (16 bits) to XLEN bits.