RISC-V Instructions

547 instructions - showing 100 per page, page 4 of 6 - click any row to view encoding, pseudocode, and full documentation.

RISC-V Unprivileged ISA Specification RISC-V Privileged Architecture Specification
By extension → 100 instructions
Mnemonic ⇅ Syntax Format ⇅ Extension ⇅ Summary
SHA256SUM0 SHA256SUM0 rd, rs1 I-Type Zk Performs the Sum0 transformation function for SHA-256.
SHA512SIG0 SHA512SIG0 rd, rs1 R-Type Zknh Performs SHA-512 Sigma0 transformation (RV64).
SHA512SIG1 SHA512SIG1 rd, rs1 R-Type Zknh Performs SHA-512 Sigma1 transformation (RV64).
SHA512SUM0 SHA512SUM0 rd, rs1 R-Type Zknh Performs SHA-512 Sum0 transformation (RV64).
SHA512SUM1 SHA512SUM1 rd, rs1 R-Type Zknh Performs SHA-512 Sum1 transformation (RV64).
SLL SLL rd, rs1, rs2 R-Type RV32I Shifts a register left by the number of bits specified in another register.
SLLI SLLI rd, rs1, shamt I-Type (Shift) RV32I Shifts a register left by a constant amount.
SLLIW SLLIW rd, rs1, shamt I-Type (Shift) RV64I Shifts the lower 32 bits of rs1 left by a constant, sign-extending the result.
SLLW SLLW rd, rs1, rs2 R-Type RV64I Performs a 32-bit logical left shift on rs1 by the amount in rs2 (lower 5 bits), sign-extending the result.
SLT SLT rd, rs1, rs2 R-Type RV32I Sets rd to 1 if rs1 < rs2 (signed), otherwise 0.
SLTI SLTI rd, rs1, imm I-Type RV32I Sets rd to 1 if rs1 < immediate (signed), otherwise 0.
SLTIU SLTIU rd, rs1, imm I-Type RV32I Sets rd to 1 if rs1 < immediate (unsigned comparison), otherwise 0.
SLTU SLTU rd, rs1, rs2 R-Type RV32I Sets rd to 1 if rs1 < rs2 (unsigned comparison), otherwise 0.
SM3P0 SM3P0 rd, rs1 R-Type Zksh Performs the P0 permutation for the SM3 hash algorithm.
SM3P1 SM3P1 rd, rs1 R-Type Zksh Performs the P1 permutation for the SM3 hash algorithm.
SM4ED SM4ED rd, rs1, rs2, bs R-Type Zksh Accelerates the SM4 block cipher (encryption/decryption round).
SM4KS SM4KS rd, rs1, rs2, bs R-Type Zksh Accelerates the SM4 key schedule generation.
SNEZ SNEZ rd, rs R-Type Pseudo Sets rd to 1 if rs is not zero, otherwise 0.
SRA SRA rd, rs1, rs2 R-Type RV32I Shifts a register right, preserving the sign bit.
SRAIW SRAIW rd, rs1, shamt I-Type (Shift) RV64I Arithmetically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result.
SRAW SRAW rd, rs1, rs2 R-Type RV64I Performs a 32-bit arithmetic right shift on rs1, sign-extending the result.
SRET SRET R-Type (System) Privileged Returns from a supervisor-mode trap handler.
SRL SRL rd, rs1, rs2 R-Type RV32I Shifts a register right, shifting in zeros.
SRLIW SRLIW rd, rs1, shamt I-Type (Shift) RV64I Logically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result.
SRLW SRLW rd, rs1, rs2 R-Type RV64I Performs a 32-bit logical right shift on rs1 by the amount in rs2, sign-extending the result.
SUB SUB rd, rs1, rs2 R-Type RV32I Subtracts rs2 from rs1.
SUBW SUBW rd, rs1, rs2 R-Type RV64I Subtracts the lower 32 bits of rs2 from rs1 and sign-extends the result to 64 bits.
SW SW rs2, offset(rs1) S-Type RV32I Stores a 32-bit word to memory.
URET URET R-Type (System) Privileged Returns from a user-mode trap handler (requires N extension).
VAADD.VV VAADD.VV vd, vs2, vs1, vm OPIVV V Computes (vs1 + vs2) >> 1 with rounding.
VAADDU.VV VAADDU.VV vd, vs2, vs1, vm OPIVV V Computes (a + b + 1) >> 1 for unsigned integers.
VADC.VVM VADC.VVM vd, vs2, vs1, v0 OPIVV V Computes vd = vs1 + vs2 + carry (v0).
VADD.VI VADD.VI vd, vs2, imm, vm OPIVI V Adds immediate to vector.
VADD.VV VADD.VV vd, vs2, vs1, vm OPIVV V Adds elements of two vector registers.
VAESDF.VV VAESDF.VV vd, vs2, vs1 OPIVV Zvkned Performs the final AES decryption round.
VAESDM.VV VAESDM.VV vd, vs2, vs1 OPIVV Zvkned Performs a middle AES decryption round.
VAESEF.VV VAESEF.VV vd, vs2, vs1 OPIVV Zvkned Performs the final AES encryption round.
VAESEM.VV VAESEM.VV vd, vs2, vs1 OPIVV Zvkned Performs a middle AES encryption round.
VAESKF1.VI VAESKF1.VI vd, vs2, uimm OPIVI Zvkned Generates the next round key for AES (Step 1).
VAESKF2.VI VAESKF2.VI vd, vs2, uimm OPIVI Zvkned Generates the next round key for AES (Step 2).
VAMOADDD.V VAMOADDD.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomically adds elements from vs2 to memory addresses (64-bit).
VAMOADDW.V VAMOADDW.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomically adds elements from vs2 to memory addresses in rs1 (indexed by vs2? No, rs1 is base, vs2 is index).
VAMOANDD.V VAMOANDD.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomically ANDs elements (64-bit).
VAMOANDW.V VAMOANDW.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomically ANDs elements.
VAMOMAXD.V VAMOMAXD.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomic Max (Signed, 64-bit).
VAMOMAXU.V VAMOMAXU.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomic Max (Unsigned, Width implicit).
VAMOMAXW.V VAMOMAXW.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomic Max (Signed).
VAMOMIND.V VAMOMIND.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomic Min (Signed, 64-bit).
VAMOMINU.V VAMOMINU.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomic Min (Unsigned, Width implicit).
VAMOMINW.V VAMOMINW.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomic Min (Signed).
VAMOORD.V VAMOORD.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomically ORs elements (64-bit).
VAMOORW.V VAMOORW.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomically ORs elements.
VAMOXORD.V VAMOXORD.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomically XORs elements (64-bit).
VAMOXORW.V VAMOXORW.V vd, (rs1), vs2, vm VAMO Zvamo (draft) Atomically XORs elements.
VAND.VI VAND.VI vd, vs2, imm, vm OPIVI V Bitwise AND with immediate.
VANDN.VV VANDN.VV vd, vs2, vs1, vm OPIVV Zvbb Computes vd = vs2 & ~vs1 (bitwise AND with inverted source).
VANDN.VX VANDN.VX vd, vs2, rs1, vm OPIVX Zvbb Computes vd = vs2 & ~rs1.
VASUB.VV VASUB.VV vd, vs2, vs1, vm OPIVV V Computes (a - b) >> 1 for signed integers.
VASUBU.VV VASUBU.VV vd, vs2, vs1, vm OPIVV V Computes (a - b) >> 1 for unsigned integers.
VBREV8.V VBREV8.V vd, vs2, vm OPIVV Zvbb Reverses the bits within each byte of the source elements.
VCLMUL.VV VCLMUL.VV vd, vs2, vs1, vm OPIVV Zvbc Performs carry-less multiplication on vector elements (GF(2^n)).
VCLMULH.VV VCLMULH.VV vd, vs2, vs1, vm OPIVV Zvbc Performs carry-less multiplication, keeping the high half.
VCLZ.V VCLZ.V vd, vs2, vm OPIVV Zvbb Counts the number of leading zero bits in each element.
VCOMPRESS.VM VCOMPRESS.VM vd, vs2, vs1 OPMVV V Compacts elements from source vector into contiguous elements in dest where the mask is 1.
VCPOP.M VCPOP.M rd, vs2, vm OPMVX V Counts set bits in the source mask register.
VCPOP.V VCPOP.V vd, vs2, vm OPIVV Zvbb Counts the number of set bits (1s) in each element.
VCTZ.V VCTZ.V vd, vs2, vm OPIVV Zvbb Counts the number of trailing zero bits in each element.
VDIV.VV VDIV.VV vd, vs2, vs1, vm OPIVV V Divides signed vector elements.
VDIVU.VV VDIVU.VV vd, vs2, vs1, vm OPIVV V Divides unsigned vector elements.
VFADD.VV VFADD.VV vd, vs2, vs1, vm OPFVV V Adds elements of two vector registers (Floating Point).
VFCLASS.V VFCLASS.V vd, vs2, vm OPFVV V Classifies elements of a float vector (NaN, Inf, etc.).
VFCVT.F.X.V VFCVT.F.X.V vd, vs2, vm OPFVV V Converts signed integer elements to floating-point.
VFCVT.X.F.V VFCVT.X.F.V vd, vs2, vm OPFVV V Converts floating-point elements to signed integers.
VFDIV.VV VFDIV.VV vd, vs2, vs1, vm OPFVV V Divides elements of two floating-point vectors.
VFIRST.M VFIRST.M rd, vs2, vm OPMVX V Finds the index of the first set bit in the mask.
VFMADD.VV VFMADD.VV vd, vs1, vs2, vm OPFVV V Computes (vs1 * vs2) + vd (overwriting vd) with single rounding.
VFMAX.VV VFMAX.VV vd, vs2, vs1, vm OPFVV V Writes the larger of two floating-point vector elements to vd.
VFMIN.VV VFMIN.VV vd, vs2, vs1, vm OPFVV V Writes the smaller of two floating-point vector elements to vd.
VFMUL.VV VFMUL.VV vd, vs2, vs1, vm OPFVV V Multiplies elements of two floating-point vectors.
VFMV.F.S VFMV.F.S fd, vs2 OPFVW V Moves element 0 of a float vector to a scalar float register.
VFMV.S.F VFMV.S.F vd, fs1 OPFVW V Moves a scalar float register to element 0 of a vector.
VFNCVT.F.F.W VFNCVT.F.F.W vd, vs2, vm OPFVV V Converts 2*N-bit floats to N-bit floats (e.g., FP32 -> FP16).
VFNCVT.X.F.W VFNCVT.X.F.W vd, vs2, vm OPFVV V Converts 2*N-bit float to N-bit signed integer.
VFREC7.V VFREC7.V vd, vs2, vm OPFVV V Computes an estimate of 1/x (7-bit precision). Used for fast division/normalization loops.
VFREDMAX.VS VFREDMAX.VS vd, vs2, vs1, vm OPFVV V Reduces a float vector to a scalar by finding the maximum element.
VFREDOSUM.VS VFREDOSUM.VS vd, vs2, vs1, vm OPFVV V Sums float vector elements in exact order (0 to vl-1).
VFREDUSUM.VS VFREDUSUM.VS vd, vs2, vs1, vm OPFVV V Reduces a float vector to a scalar by summing elements (Order not preserved, faster).
VFRSQRT7.V VFRSQRT7.V vd, vs2, vm OPFVV V Computes an estimate of 1/sqrt(x). Critical for vector normalization.
VFSGNJ.VV VFSGNJ.VV vd, vs2, vs1, vm OPFVV V Injects the sign of vs2 into vs1 (Copy Sign).
VFSQRT.V VFSQRT.V vd, vs2, vm OPFVV V Computes the square root of elements in a floating-point vector.
VFWADD.VV VFWADD.VV vd, vs2, vs1, vm OPFVV V Adds N-bit floats to produce 2*N-bit float results (e.g., FP16 + FP16 -> FP32).
VFWCVT.F.F.V VFWCVT.F.F.V vd, vs2, vm OPFVV V Converts N-bit floats to 2*N-bit floats (e.g., FP16 -> FP32).
VFWCVT.F.X.V VFWCVT.F.X.V vd, vs2, vm OPFVV V Converts N-bit integers to 2*N-bit floats (e.g., Int16 -> FP32).
VFWCVT.X.F.V VFWCVT.X.F.V vd, vs2, vm OPFVV V Converts N-bit float to 2*N-bit signed integer.
VFWMUL.VV VFWMUL.VV vd, vs2, vs1, vm OPFVV V Multiplies N-bit floats to produce 2*N-bit float results.
VFWREDOSUM.VS VFWREDOSUM.VS vd, vs2, vs1, vm OPFVV V Sums N-bit floats into 2*N-bit scalar accumulator (Ordered).
VFWREDUSUM.VS VFWREDUSUM.VS vd, vs2, vs1, vm OPFVV V Sums N-bit floats into 2*N-bit scalar accumulator (Unordered).
VGHSH.VV VGHSH.VV vd, vs2, vs1 OPIVV Zvkg Performs GHASH multiply-add for AES-GCM.
VID.V VID.V vd, vm OPMVV V Writes the element index (0, 1, 2...) to the destination.
VIOTA.M VIOTA.M vd, vs2, vm OPMVV V Writes the index of the active element to the destination. Useful for parallel prefix sums.