RISC-V Instructions
547 instructions - showing 100 per page, page 2 of 6 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| CBO.ZERO | CBO.ZERO (rs1) | I-Type | Zicboz | Zeros a cache block corresponding to the address in rs1. |
| CLMUL | CLMUL rd, rs1, rs2 | R-Type | Zbc | Performs carry-less multiplication of the lower bits of rs1 and rs2. Used for CRC and GCM (crypto). |
| CLZ | CLZ rd, rs1 | I-Type | Zbb | Counts the number of 0 bits at the MSB end of the register. |
| CM.POP | CM.POP {reg_list}, stack_adj | Push/Pop | Zcmp | Pops multiple registers from the stack and restores sp. |
| CM.PUSH | CM.PUSH {reg_list}, -stack_adj | Push/Pop | Zcmp | Pushes multiple registers (ra, s0-s11) to the stack and adjusts sp. Critical for small code size. |
| CPOP | CPOP rd, rs1 | I-Type | Zbb | Counts the number of set bits (1s) in the register. |
| CSRC | CSRC csr, rs | I-Type | Pseudo | Clears bits in a CSR (bitwise AND NOT). |
| CSRR | CSRR rd, csr | I-Type | Pseudo | Reads the value of a CSR into a register. |
| CSRRC | CSRRC rd, csr, rs1 | I-Type | Zicsr | Reads the old value of the CSR, then clears bits in the CSR based on the mask in rs1. |
| CSRRCI | CSRRCI rd, csr, uimm | I-Type | Zicsr | Clears bits in a CSR using a 5-bit unsigned immediate. |
| CSRRS | CSRRS rd, csr, rs1 | I-Type | Zicsr | Reads the value of the CSR into rd, then bitwise ORs the value in rs1 into the CSR (setting bits). |
| CSRRSI | CSRRSI rd, csr, uimm | I-Type | Zicsr | Sets bits in a CSR using a 5-bit unsigned immediate. |
| CSRRW | CSRRW rd, csr, rs1 | I-Type | Zicsr | Atomically swaps values in the CSRs. Reads the old value of the CSR into rd, then writes rs1 to the CSR. |
| CSRRWI | CSRRWI rd, csr, uimm | I-Type | Zicsr | Updates a CSR using a 5-bit unsigned immediate (zimm) instead of a register. |
| CSRS | CSRS csr, rs | I-Type | Pseudo | Sets bits in a CSR (bitwise OR). |
| CSRW | CSRW csr, rs | I-Type | Pseudo | Writes a register value to a CSR. |
| CTZ | CTZ rd, rs1 | I-Type | Zbb | Counts the number of 0 bits at the LSB end of the register. |
| CZERO.EQZ | CZERO.EQZ rd, rs1, rs2 | R-Type | Zicond | Moves rs1 to rd if rs2 is non-zero, otherwise sets rd to zero. |
| CZERO.NEZ | CZERO.NEZ rd, rs1, rs2 | R-Type | Zicond | Moves rs1 to rd if rs2 is zero, otherwise sets rd to zero. |
| DIV | DIV rd, rs1, rs2 | R-Type | M | Performs signed integer division. |
| DIVU | DIVU rd, rs1, rs2 | R-Type | M | Performs unsigned integer division. |
| DIVUW | DIVUW rd, rs1, rs2 | R-Type | M | Performs 32-bit unsigned division of rs1 by rs2, sign-extending the result. |
| DIVW | DIVW rd, rs1, rs2 | R-Type | M | Performs 32-bit signed division of rs1 by rs2, sign-extending the result. |
| DRET | DRET | R-Type (System) | Privileged | Returns from Debug Mode to the mode defined in the 'dcsr' register. |
| EBREAK | EBREAK | I-Type | RV32I | Used by debuggers to cause control to be transferred back to a debugging environment. |
| ECALL | ECALL | I-Type | RV32I | Generates an environment call exception (system call). |
| FADD.D | FADD.D rd, rs1, rs2 | R-Type | D | Performs double-precision floating-point addition. |
| FADD.H | FADD.H rd, rs1, rs2 | R-Type | Zfh | Performs 16-bit floating-point addition. |
| FADD.S | FADD.S rd, rs1, rs2 | R-Type | F | Performs single-precision floating-point addition. |
| FCLASS.D | FCLASS.D rd, rs1 | R-Type | D | Examines a double-precision register and generates a classification bitmask. |
| FCLASS.H | FCLASS.H rd, rs1 | R-Type | Zfh | Examines a 16-bit floating-point number and generates a classification bitmask. |
| FCLASS.S | FCLASS.S rd, rs1 | R-Type | F | Examines the value in a float register and generates a 10-bit bitmask indicating its class (NaN, Inf, Zero, Normal, etc.). |
| FCVT.D.L | FCVT.D.L rd, rs1 | I-Type (Float) | D | Converts a 64-bit signed integer to a double-precision float. |
| FCVT.D.LU | FCVT.D.LU rd, rs1 | I-Type (Float) | D | Converts a 64-bit unsigned integer to a double-precision float. |
| FCVT.D.S | FCVT.D.S rd, rs1 | I-Type (Float) | D | Converts a single-precision float to a double-precision float. |
| FCVT.D.W | FCVT.D.W rd, rs1 | I-Type (Float) | D | Converts a 32-bit signed integer to a double-precision float. |
| FCVT.D.WU | FCVT.D.WU rd, rs1 | I-Type (Float) | D | Converts a 32-bit unsigned integer to a double-precision float. |
| FCVT.H.S | FCVT.H.S rd, rs1 | I-Type (Float) | Zfh | Converts a 32-bit single-precision float to a 16-bit half-precision float. |
| FCVT.H.W | FCVT.H.W rd, rs1 | I-Type (Float) | Zfh | Converts a 32-bit signed integer to a 16-bit floating-point number. |
| FCVT.H.WU | FCVT.H.WU rd, rs1 | I-Type (Float) | Zfh | Converts a 32-bit unsigned integer to a 16-bit floating-point number. |
| FCVT.L.D | FCVT.L.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a 64-bit signed integer. |
| FCVT.L.S | FCVT.L.S rd, rs1 | I-Type (Float) | F | Converts a single-precision float to a 64-bit signed integer. |
| FCVT.LU.D | FCVT.LU.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a 64-bit unsigned integer. |
| FCVT.LU.S | FCVT.LU.S rd, rs1 | I-Type (Float) | F | Converts a single-precision float to a 64-bit unsigned integer. |
| FCVT.S.D | FCVT.S.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a single-precision float. |
| FCVT.S.H | FCVT.S.H rd, rs1 | I-Type (Float) | Zfh | Converts a 16-bit half-precision float to a 32-bit single-precision float. |
| FCVT.S.L | FCVT.S.L rd, rs1 | I-Type (Float) | F | Converts a 64-bit signed integer (Long) to a single-precision float. |
| FCVT.S.LU | FCVT.S.LU rd, rs1 | I-Type (Float) | F | Converts a 64-bit unsigned integer to a single-precision float. |
| FCVT.S.W | FCVT.S.W rd, rs1 | I-Type (Float) | F | Converts a signed 32-bit integer to a single-precision floating-point number. |
| FCVT.S.WU | FCVT.S.WU rd, rs1 | I-Type (Float) | F | Converts a 32-bit unsigned integer to a single-precision float. |
| FCVT.W.D | FCVT.W.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a 32-bit signed integer. |
| FCVT.W.H | FCVT.W.H rd, rs1 | I-Type (Float) | Zfh | Converts a 16-bit floating-point number to a 32-bit signed integer. |
| FCVT.W.S | FCVT.W.S rd, rs1 | I-Type (Float) | F | Converts a single-precision floating-point number to a signed 32-bit integer. |
| FCVT.WU.D | FCVT.WU.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a 32-bit unsigned integer. |
| FCVT.WU.H | FCVT.WU.H rd, rs1 | I-Type (Float) | Zfh | Converts a 16-bit floating-point number to a 32-bit unsigned integer. |
| FCVT.WU.S | FCVT.WU.S rd, rs1 | I-Type (Float) | F | Converts a single-precision float to a 32-bit unsigned integer. |
| FDIV.D | FDIV.D rd, rs1, rs2 | R-Type | D | Performs double-precision floating-point division. |
| FDIV.H | FDIV.H rd, rs1, rs2 | R-Type | Zfh | Performs 16-bit floating-point division. |
| FDIV.S | FDIV.S rd, rs1, rs2 | R-Type | F | Performs single-precision floating-point division. |
| FENCE | FENCE pred, succ | I-Type | RV32I | Orders device I/O and memory accesses. |
| FENCE.I | FENCE.I | I-Type | Zifencei | Synchronizes the instruction cache with the data cache (used after self-modifying code). |
| FEQ.D | FEQ.D rd, rs1, rs2 | R-Type | D | Sets integer rd to 1 if double rs1 equals double rs2, else 0. |
| FEQ.H | FEQ.H rd, rs1, rs2 | R-Type | Zfh | Sets integer rd to 1 if half-precision rs1 equals rs2, else 0. |
| FEQ.S | FEQ.S rd, rs1, rs2 | R-Type | F | Sets integer rd to 1 if float rs1 equals float rs2, else 0. |
| FLD | FLD rd, offset(rs1) | I-Type | D | Loads a 64-bit double-precision floating-point value from memory. |
| FLE.D | FLE.D rd, rs1, rs2 | R-Type | D | Sets integer rd to 1 if double rs1 is less than or equal to double rs2, else 0. |
| FLE.H | FLE.H rd, rs1, rs2 | R-Type | Zfh | Sets integer rd to 1 if half-precision rs1 is less than or equal to rs2, else 0. |
| FLE.S | FLE.S rd, rs1, rs2 | R-Type | F | Sets integer rd to 1 if float rs1 is less than or equal to float rs2, else 0. |
| FLH | FLH rd, offset(rs1) | I-Type | Zfh | Loads a 16-bit half-precision float from memory. |
| FLI.D | FLI.D rd, rs1 | R-Type | Zfa | Loads a common double-precision constant into a register. |
| FLI.H | FLI.H rd, rs1 | R-Type | Zfa | Loads a common half-precision constant into a register. |
| FLI.S | FLI.S rd, rs1 | R-Type | Zfa | Loads a common floating-point constant (e.g., 1.0, 0.5, PI) into a register from a small table. |
| FLT.D | FLT.D rd, rs1, rs2 | R-Type | D | Sets integer rd to 1 if double rs1 is less than double rs2, else 0. |
| FLT.H | FLT.H rd, rs1, rs2 | R-Type | Zfh | Sets integer rd to 1 if half-precision rs1 is less than rs2, else 0. |
| FLT.S | FLT.S rd, rs1, rs2 | R-Type | F | Sets integer rd to 1 if float rs1 is less than float rs2, else 0. |
| FLW | FLW rd, offset(rs1) | I-Type | F | Loads a single-precision floating-point value from memory. |
| FMADD.D | FMADD.D rd, rs1, rs2, rs3 | R4-Type | D | Computes (rs1 * rs2) + rs3 with a single rounding (64-bit). |
| FMADD.H | FMADD.H rd, rs1, rs2, rs3 | R4-Type | Zfh | Computes (rs1 * rs2) + rs3 with single rounding (16-bit). |
| FMADD.S | FMADD.S rd, rs1, rs2, rs3 | R4-Type | F | Computes (rs1 * rs2) + rs3 with a single rounding. |
| FMAX.D | FMAX.D rd, rs1, rs2 | R-Type | D | Writes the larger of two double-precision floating-point values to rd. |
| FMAX.H | FMAX.H rd, rs1, rs2 | R-Type | Zfh | Writes the larger of two 16-bit floating-point values to rd. |
| FMAX.S | FMAX.S rd, rs1, rs2 | R-Type | F | Writes the larger of two single-precision floating-point values to rd. |
| FMAXM.S | FMAXM.S rd, rs1, rs2 | R-Type | Zfa | Maximum of two floats, treating +0.0 as larger than -0.0. |
| FMIN.D | FMIN.D rd, rs1, rs2 | R-Type | D | Writes the smaller of two double-precision floating-point values to rd. |
| FMIN.H | FMIN.H rd, rs1, rs2 | R-Type | Zfh | Writes the smaller of two 16-bit floating-point values to rd. |
| FMIN.S | FMIN.S rd, rs1, rs2 | R-Type | F | Writes the smaller of two single-precision floating-point values to rd. |
| FMINM.S | FMINM.S rd, rs1, rs2 | R-Type | Zfa | Minimum of two floats, treating -0.0 as smaller than +0.0 (canonicalize NaNs). |
| FMSUB.D | FMSUB.D rd, rs1, rs2, rs3 | R4-Type | D | Computes (rs1 * rs2) - rs3 with a single rounding (Double). |
| FMSUB.H | FMSUB.H rd, rs1, rs2, rs3 | R4-Type | Zfh | Computes (rs1 * rs2) - rs3 with single rounding (16-bit). |
| FMSUB.S | FMSUB.S rd, rs1, rs2, rs3 | R4-Type | F | Computes (rs1 * rs2) - rs3 with a single rounding. |
| FMUL.D | FMUL.D rd, rs1, rs2 | R-Type | D | Performs double-precision floating-point multiplication. |
| FMUL.H | FMUL.H rd, rs1, rs2 | R-Type | Zfh | Performs 16-bit floating-point multiplication. |
| FMUL.S | FMUL.S rd, rs1, rs2 | R-Type | F | Performs single-precision floating-point multiplication. |
| FMV.D.X | FMV.D.X rd, rs1 | I-Type (Float) | D | Moves the bit pattern of a 64-bit integer register to a floating-point register (RV64). |
| FMV.W.X | FMV.W.X rd, rs1 | I-Type (Float) | F | Moves the bit pattern of an integer register to a floating-point register. |
| FMV.X.D | FMV.X.D rd, rs1 | I-Type (Float) | D | Moves the bit pattern of a 64-bit floating-point register to an integer register (RV64). |
| FMV.X.W | FMV.X.W rd, rs1 | I-Type (Float) | F | Moves the bit pattern of a floating-point register to an integer register. |
| FNMADD.D | FNMADD.D rd, rs1, rs2, rs3 | R4-Type | D | Computes -(rs1 * rs2) - rs3 with a single rounding (Double). |
| FNMADD.H | FNMADD.H rd, rs1, rs2, rs3 | R4-Type | Zfh | Computes -(rs1 * rs2) - rs3 with single rounding (16-bit). |
| FNMADD.S | FNMADD.S rd, rs1, rs2, rs3 | R4-Type | F | Computes -(rs1 * rs2) - rs3 with a single rounding. |