RISC-V Instructions
547 instructions - showing 100 per page, page 3 of 6 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| FNMSUB.D | FNMSUB.D rd, rs1, rs2, rs3 | R4-Type | D | Computes -(rs1 * rs2) + rs3 with a single rounding (Double). |
| FNMSUB.H | FNMSUB.H rd, rs1, rs2, rs3 | R4-Type | Zfh | Computes -(rs1 * rs2) + rs3 with single rounding (16-bit). |
| FNMSUB.S | FNMSUB.S rd, rs1, rs2, rs3 | R4-Type | F | Computes -(rs1 * rs2) + rs3 with a single rounding. |
| FROUND.S | FROUND.S rd, rs1, rm | I-Type | Zfa | Rounds a float to the nearest integer value (returned as a float). |
| FSD | FSD rs2, offset(rs1) | S-Type | D | Stores a 64-bit double-precision floating-point value to memory. |
| FSGNJ.D | FSGNJ.D rd, rs1, rs2 | R-Type | D | Injects the sign of rs2 into rs1 (Double Precision). |
| FSGNJ.H | FSGNJ.H rd, rs1, rs2 | R-Type | Zfh | Injects the sign of rs2 into rs1 (16-bit). |
| FSGNJ.S | FSGNJ.S rd, rs1, rs2 | R-Type | F | Injects the sign of rs2 into rs1. Used to copy values or manipulate signs. |
| FSGNJN.D | FSGNJN.D rd, rs1, rs2 | R-Type | D | Injects the *negated* sign of rs2 into rs1 (Double Precision). |
| FSGNJN.H | FSGNJN.H rd, rs1, rs2 | R-Type | Zfh | Injects the negated sign of rs2 into rs1 (16-bit). |
| FSGNJN.S | FSGNJN.S rd, rs1, rs2 | R-Type | F | Injects the *negated* sign of rs2 into rs1. Used for negation and absolute value. |
| FSGNJX.D | FSGNJX.D rd, rs1, rs2 | R-Type | D | Injects the XOR of signs of rs1 and rs2 (Double Precision). |
| FSGNJX.H | FSGNJX.H rd, rs1, rs2 | R-Type | Zfh | Injects the XOR of signs of rs1 and rs2 (16-bit). |
| FSGNJX.S | FSGNJX.S rd, rs1, rs2 | R-Type | F | Injects the XOR of signs of rs1 and rs2. Used to copy sign. |
| FSH | FSH rs2, offset(rs1) | S-Type | Zfh | Stores a 16-bit half-precision float to memory. |
| FSQRT.D | FSQRT.D rd, rs1 | I-Type (Float) | D | Computes the square root of a double-precision floating-point number. |
| FSQRT.H | FSQRT.H rd, rs1 | I-Type (Float) | Zfh | Computes the square root of a 16-bit floating-point number. |
| FSQRT.S | FSQRT.S rd, rs1 | I-Type (Float) | F | Computes the square root of a single-precision floating-point number. |
| FSUB.D | FSUB.D rd, rs1, rs2 | R-Type | D | Performs double-precision floating-point subtraction. |
| FSUB.H | FSUB.H rd, rs1, rs2 | R-Type | Zfh | Performs 16-bit floating-point subtraction. |
| FSUB.S | FSUB.S rd, rs1, rs2 | R-Type | F | Performs single-precision floating-point subtraction. |
| FSW | FSW rs2, offset(rs1) | S-Type | F | Stores a single-precision floating-point value to memory. |
| HFENCE.GVMA | HFENCE.GVMA rs1, rs2 | R-Type | H | Synchronizes updates to guest physical address translation data structures. |
| HFENCE.VVMA | HFENCE.VVMA rs1, rs2 | R-Type | H | Synchronizes updates to VS-stage address translation data structures. |
| HLV.B | HLV.B rd, (rs1) | R-Type (System) | H | Loads a byte from Guest Physical Memory (VS-stage translation only). |
| HLV.D | HLV.D rd, (rs1) | R-Type (System) | H | Loads a doubleword from guest physical memory. |
| HLV.W | HLV.W rd, (rs1) | R-Type (System) | H | Loads a word from Guest Physical Memory (VS-stage translation only). |
| HLV.WU | HLV.WU rd, (rs1) | R-Type (System) | H | Loads a word from guest physical memory (unsigned). |
| HSV.B | HSV.B rs2, (rs1) | R-Type (System) | H | Stores a byte to Guest Physical Memory. |
| HSV.D | HSV.D rs2, (rs1) | R-Type (System) | H | Stores a doubleword to guest physical memory. |
| HSV.W | HSV.W rs2, (rs1) | R-Type (System) | H | Stores a word to Guest Physical Memory. |
| J | J offset | J-Type | Pseudo | Unconditionally jumps to a target offset. |
| JAL | JAL rd, offset | J-Type | RV32I | Jumps to an offset relative to PC and saves the return address (PC+4) to rd. |
| JALR | JALR rd, offset(rs1) | I-Type | RV32I | Jumps to address in rs1 + offset, saving return address to rd. |
| JR | JR rs | I-Type | Pseudo | Unconditionally jumps to an address held in a register. |
| LB | LB rd, offset(rs1) | I-Type | RV32I | Loads an 8-bit byte from memory and sign-extends it to the register width. |
| LBU | LBU rd, offset(rs1) | I-Type | RV32I | Loads an 8-bit byte from memory and zero-extends it. |
| LD | LD rd, offset(rs1) | I-Type | RV64I | Loads a 64-bit doubleword from memory. |
| LH | LH rd, offset(rs1) | I-Type | RV32I | Loads a 16-bit halfword from memory and sign-extends it. |
| LHU | LHU rd, offset(rs1) | I-Type | RV32I | Loads a 16-bit halfword from memory and zero-extends it. |
| LI | LI rd, imm | U-Type | Pseudo | Loads an arbitrary immediate value into a register. |
| LR.D | LR.D rd, (rs1) | R-Type (Atomic) | A | Loads a doubleword from memory and registers a reservation set. |
| LR.W | LR.W rd, (rs1) | R-Type (Atomic) | A | Loads a word from memory and registers a reservation set for the address. |
| LUI | LUI rd, imm | U-Type | RV32I | Loads the 20-bit immediate into the upper 20 bits of the register (lower 12 bits are zero). |
| LW | LW rd, offset(rs1) | I-Type | RV32I | Loads a 32-bit word from memory and sign-extends it to 64 bits. |
| LWU | LWU rd, offset(rs1) | I-Type | RV64I | Loads a 32-bit word from memory and zero-extends it to 64 bits. |
| MAX | MAX rd, rs1, rs2 | R-Type | Zbb | Computes the signed maximum of two registers. |
| MAXU | MAXU rd, rs1, rs2 | R-Type | Zbb | Computes the maximum of two unsigned integers. |
| MIN | MIN rd, rs1, rs2 | R-Type | Zbb | Computes the signed minimum of two registers. |
| MINU | MINU rd, rs1, rs2 | R-Type | Zbb | Computes the minimum of two unsigned integers. |
| MRET | MRET | R-Type (System) | Privileged | Returns from a machine-mode trap handler. |
| MUL | MUL rd, rs1, rs2 | R-Type | M | Performs a 32-bit (or 64-bit) multiplication of rs1 and rs2 and stores the lower bits in rd. |
| MULH | MULH rd, rs1, rs2 | R-Type | M | Performs a signed multiplication and stores the upper bits of the result. |
| MULHSU | MULHSU rd, rs1, rs2 | R-Type | M | Multiplies signed rs1 by unsigned rs2 and returns the upper XLEN bits. |
| MULHU | MULHU rd, rs1, rs2 | R-Type | M | Performs unsigned multiplication and returns the upper XLEN bits. |
| MULW | MULW rd, rs1, rs2 | R-Type | M | Performs 32-bit multiplication of rs1 and rs2, sign-extending the 32-bit result to 64 bits. |
| MV | MV rd, rs | I-Type | Pseudo | Copies the value of one register into another. |
| NEG | NEG rd, rs | R-Type | Pseudo | Computes the two's complement negation (arithmetic negative). |
| NOP | NOP | I-Type | Pseudo | Performs no operation. Used for alignment or timing delays. |
| NOT | NOT rd, rs | I-Type | Pseudo | Computes the bitwise logical negation (one's complement). |
| NTL.ALL | NTL.ALL | R-Type | Zihintntl | Hint that the subsequent store should bypass all cache levels. |
| NTL.P1 | NTL.P1 | R-Type | Zihintntl | Hint that the target cache block will be needed, but is likely to be discarded after use (Stream data). |
| NTL.PALL | NTL.PALL | R-Type | Zihintntl | Hint that the target data should not be cached in any level of the cache hierarchy (Transient data). |
| NTL.S1 | NTL.S1 | R-Type | Zihintntl | Hint that the subsequent store is non-temporal (Streaming Store). |
| OR | OR rd, rs1, rs2 | R-Type | RV32I | Performs a bitwise logical OR operation. |
| ORC.B | ORC.B rd, rs1 | I-Type | Zbb | Sets each byte of the result to 0xFF if the corresponding byte of the source is non-zero, else 0x00. |
| ORI | ORI rd, rs1, imm | I-Type | RV32I | Performs a bitwise logical OR with a sign-extended immediate. |
| ORN | ORN rd, rs1, rs2 | R-Type | Zbb | Performs bitwise OR with the bitwise negation of rs2 (rs1 | ~rs2). |
| PACK | PACK rd, rs1, rs2 | R-Type | Zbkb | Packs the lower halves of rs1 and rs2 into rd. |
| PACKH | PACKH rd, rs1, rs2 | R-Type | Zbkb | Packs the lower bytes of rs1 and rs2 into a 16-bit value. |
| PAUSE | PAUSE | I-Type (Hint) | Zihintpause | Hints that the current hart is in a spin-wait loop, allowing the hardware to reduce power consumption or yield resources. |
| PREFETCH.I | PREFETCH.I offset(rs1) | S-Type (Hint) | Zicbop | Hints to hardware to bring the cache block containing the instruction at the address into the instruction cache. |
| PREFETCH.R | PREFETCH.R offset(rs1) | S-Type (Hint) | Zicbop | Hints to hardware to bring the cache block at the address into the data cache for reading. |
| PREFETCH.W | PREFETCH.W offset(rs1) | S-Type (Hint) | Zicbop | Hints to hardware to bring the cache block at the address into the data cache for writing (exclusive ownership). |
| RDCYCLE | RDCYCLE rd | I-Type | Pseudo | Reads the lower 32/64 bits of the cycle counter. |
| RDINSTRET | RDINSTRET rd | I-Type | Pseudo | Reads the count of instructions retired (completed). |
| RDTIME | RDTIME rd | I-Type | Pseudo | Reads the lower 32/64 bits of the real-time clock. |
| REM | REM rd, rs1, rs2 | R-Type | M | Computes the signed remainder of division. |
| REMU | REMU rd, rs1, rs2 | R-Type | M | Computes the unsigned remainder of division. |
| REMUW | REMUW rd, rs1, rs2 | R-Type | M | Computes the remainder of 32-bit unsigned division, sign-extending the result. |
| REMW | REMW rd, rs1, rs2 | R-Type | M | Computes the remainder of 32-bit signed division, sign-extending the result. |
| RET | RET | I-Type | Pseudo | Returns from a subroutine call. |
| REV8 | REV8 rd, rs1 | I-Type | Zbb | Reverses the order of bytes in a register (Endian swap). |
| ROL | ROL rd, rs1, rs2 | R-Type | Zbb | Rotates the bits in rs1 left by the amount in rs2. |
| ROR | ROR rd, rs1, rs2 | R-Type | Zbb | Rotates the bits in rs1 right by the amount in rs2. |
| SB | SB rs2, offset(rs1) | S-Type | RV32I | Stores the lowest 8 bits of a register to memory. |
| SC.D | SC.D rd, rs2, (rs1) | R-Type (Atomic) | A | Conditionally stores a 64-bit value to memory if the reservation is valid. |
| SC.W | SC.W rd, rs2, (rs1) | R-Type (Atomic) | A | Conditionally stores a word to memory if the reservation (from LR) is still valid. |
| SD | SD rs2, offset(rs1) | S-Type | RV64I | Stores a 64-bit doubleword to memory. |
| SEQZ | SEQZ rd, rs | I-Type | Pseudo | Sets rd to 1 if rs is zero, otherwise 0. |
| SEXT.B | SEXT.B rd, rs1 | I-Type | Zbb | Sign-extends the lowest byte (8 bits) to XLEN bits. |
| SEXT.H | SEXT.H rd, rs1 | I-Type | Zbb | Sign-extends the lowest halfword (16 bits) to XLEN bits. |
| SFENCE.INVAL.IR | SFENCE.INVAL.IR | R-Type (System) | Svinval | Invalidates a range of address translations based on ASID and Virtual Address. |
| SFENCE.VMA | SFENCE.VMA rs1, rs2 | R-Type (System) | Privileged | Synchronizes updates to in-memory address translation data structures (TLB flush). |
| SFENCE.W.INVAL | SFENCE.W.INVAL | R-Type (System) | Svinval | Orders previous stores against subsequent local instruction fetches or translations (Memory Management). |
| SH | SH rs2, offset(rs1) | S-Type | RV32I | Stores the lowest 16 bits of a register to memory. |
| SH1ADD | SH1ADD rd, rs1, rs2 | R-Type | Zba | Shifts rs1 left by 1 and adds rs2. Used for calculating addresses of 16-bit elements. |
| SH2ADD | SH2ADD rd, rs1, rs2 | R-Type | Zba | Shifts rs1 left by 2 and adds rs2. Used for calculating addresses of 32-bit elements. |
| SH3ADD | SH3ADD rd, rs1, rs2 | R-Type | Zba | Shifts rs1 left by 3 and adds rs2. Used for calculating addresses of 64-bit elements. |
| SHA256SIG0 | SHA256SIG0 rd, rs1 | I-Type | Zk | Performs the Sigma0 transformation function for SHA-256. |