x86 Instructions

957 instructions - showing 100 per page, page 3 of 10 - click any row to view encoding, pseudocode, and full documentation.

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Intrinsics → By extension → 100 instructions
Mnemonic ⇅ Syntax Format ⇅ Extension ⇅ Summary
fstp FSTP m32fp/m64fp/m80fp Legacy x87 FPU Copies ST(0) to destination and pops the register stack.
fstsw FSTSW AX Legacy x87 FPU Stores FPU status word to AX or memory.
fsub FSUB m32fp/m64fp Legacy x87 FPU Subtracts src from dest.
fucom FUCOM ST(i) Legacy x87 FPU Compares ST(0) with source (supports NaNs).
fxch FXCH ST(i) Legacy x87 FPU Exchanges contents of ST(0) and ST(i).
fxtract FXTRACT Legacy x87 FPU Separates exponent and significand of ST(0).
fyl2x FYL2X Legacy x87 FPU Computes ST(1) * log2(ST(0)).
fyl2xp1 FYL2XP1 Legacy x87 FPU Computes ST(1) * log2(ST(0) + 1).
getsec GETSEC Legacy SMX Entry point for Safer Mode Extensions (Trusted Execution).
gf2p8affineinvqb GF2P8AFFINEINVQB xmm1, xmm2/m128, imm8 VEX GFNI Computes inverse affine transformation in GF(2^8).
gf2p8affineqb GF2P8AFFINEQB xmm1, xmm2/m128, imm8 VEX GFNI Computes affine transformation in GF(2^8).
gf2p8mulb GF2P8MULB xmm1, xmm2/m128 VEX GFNI Multiplies bytes in GF(2^8).
haddpd HADDPD xmm1, xmm2/m128 SSE3 SSE3 Adds adjacent double-precision elements horizontally.
haddps HADDPS xmm1, xmm2/m128 SSE3 SSE3 Adds adjacent float elements horizontally.
hlt HLT Legacy Base Stops instruction execution and places processor in HALT state.
hreset HRESET imm8 Legacy HRESET Resets processor history (prediction) structures.
hsubpd HSUBPD xmm1, xmm2/m128 SSE3 SSE3 Subtracts adjacent double-precision elements horizontally.
hsubps HSUBPS xmm1, xmm2/m128 SSE3 SSE3 Subtracts adjacent single-precision elements horizontally.
idiv IDIV r/m Legacy Base Signed divide (AX / src).
imul IMUL r, r/m Legacy Base Signed multiply.
in IN AL, imm8 Legacy Base Reads data from an I/O port into AL/AX/EAX.
in IN AL/AX/EAX, DX Legacy Base Reads data from I/O port specified in DX.
inc INC r/m Legacy Base Increments the operand by 1.
incsspq INCSSPQ r64 Legacy CET-SS Adjusts the shadow stack pointer.
ins INSB Legacy Base Reads string from I/O port to memory at [EDI].
insd INSD Legacy Base Reads doubleword from I/O port to memory at [EDI].
insertps INSERTPS xmm1, xmm2/m32, imm8 SSE4.1 SSE4.1 Inserts a single float into a specific index of XMM.
insertq INSERTQ xmm1, xmm2 SSE4a SSE4a Inserts bit field into register (AMD SSE4a).
insw INSW Legacy Base Reads word from I/O port to memory at [EDI].
int INT imm8 Legacy Base Calls to interrupt procedure.
int1 INT1 Legacy Base Single byte opcode (0xF1) used for In-Circuit Emulation.
int3 INT3 Legacy Base Calls to interrupt vector 3 (Debugger breakpoint).
invd INVD System System Flushes internal caches without writing back data (Privileged).
invept INVEPT r64, m128 VMX VMX (EPT) Invalidates Extended Page Table entries.
invlpg INVLPG m System System Invalidates a specific TLB entry (Privileged).
invlpga INVLPGA SVM SVM Invalidates TLB entry for specific ASID (AMD SVM).
invpcid INVPCID r32, m128 Legacy INVPCID Invalidates TLB entries based on PCID.
invvpid INVVPID r64, m128 VMX VMX (VPID) Invalidates TLB entries based on Virtual Processor ID.
iret IRET Legacy Base Returns from an interrupt, exception, or task handler.
iretd IRETD Legacy Base Returns from interrupt (32-bit operand size).
iretq IRETQ Legacy Base (64-bit) Returns from interrupt (64-bit operand size).
ja JA rel Legacy Base Jump if CF=0 and ZF=0 (Unsigned >).
jb JB rel Legacy Base Jump if CF=1 (Unsigned <).
je JE rel Legacy Base Jump if ZF=1 (Same as JZ).
jecxz JECXZ rel Legacy Base Jumps if ECX register is 0.
jg JG rel Legacy Base Jump if ZF=0 and SF=OF (Signed >).
jl JL rel Legacy Base Jump if SF!=OF (Signed <).
jmp JMP rel Legacy Base Unconditional jump to target.
jne JNE rel Legacy Base Jump if ZF=0 (Same as JNZ).
jno JNO rel Legacy Base Jump near if overflow flag is 0.
jnp JNP rel Legacy Base Jump near if parity flag is 0 (Odd parity).
jns JNS rel Legacy Base Jump near if sign flag is 0 (Positive).
jo JO rel Legacy Base Jump near if overflow flag is 1.
jp JP rel Legacy Base Jump near if parity flag is 1 (Even parity).
js JS rel Legacy Base Jump near if sign flag is 1 (Negative).
kaddb KADDB k1, k2, k3 EVEX AVX-512DQ Adds two 8-bit mask registers.
kaddw KADDW k1, k2, k3 EVEX AVX-512DQ Adds two 16-bit mask registers.
kandnw KANDNW k1, k2, k3 EVEX AVX-512 Bitwise AND NOT of 16-bit masks.
kandq KANDQ k1, k2, k3 EVEX AVX-512BW Bitwise AND of 64-bit mask registers.
kandw KANDW k1, k2, k3 EVEX AVX-512 Bitwise AND of 16-bit masks.
kmovq KMOVQ k1, k2/m64 EVEX AVX-512BW Moves 64-bit mask to/from k-register.
kmovw KMOVW k1, k2/m16 EVEX AVX-512 Moves 16-bit mask to/from k-register.
knotb KNOTB k1, k2 EVEX AVX-512DQ Bitwise NOT of 8-bit mask.
knotd KNOTD k1, k2 EVEX AVX-512BW Bitwise NOT of 32-bit mask.
knotq KNOTQ k1, k2 EVEX AVX-512BW Bitwise NOT of 64-bit mask register.
knotw KNOTW k1, k2 EVEX AVX-512 Bitwise NOT of 16-bit mask.
korb KORB k1, k2, k3 EVEX AVX-512DQ Bitwise OR of 8-bit masks.
kord KORD k1, k2, k3 EVEX AVX-512BW Bitwise OR of 32-bit masks.
korq KORQ k1, k2, k3 EVEX AVX-512BW Bitwise OR of 64-bit mask registers.
kortestb KORTESTB k1, k2 EVEX AVX-512DQ ORs 8-bit masks and sets EFLAGS (ZF/CF).
kortestq KORTESTQ k1, k2 EVEX AVX-512BW ORs 64-bit masks and sets EFLAGS (ZF/CF).
kortestw KORTESTW k1, k2 EVEX AVX-512 ORs two masks and sets EFLAGS (ZF, CF) based on result.
korw KORW k1, k2, k3 EVEX AVX-512 Bitwise OR of 16-bit masks.
kshiftlb KSHIFTLB k1, k2, imm8 EVEX AVX-512DQ Logically shifts 8-bit mask left.
kshiftld KSHIFTLD k1, k2, imm8 EVEX AVX-512BW Logically shifts 32-bit mask left.
kshiftlq KSHIFTLQ k1, k2, imm8 EVEX AVX-512BW Logically shifts 64-bit mask left.
kshiftlw KSHIFTLW k1, k2, imm8 EVEX AVX-512F Logically shifts 16-bit mask left.
kshiftrb KSHIFTRB k1, k2, imm8 EVEX AVX-512DQ Logically shifts 8-bit mask right.
kshiftrd KSHIFTRD k1, k2, imm8 EVEX AVX-512BW Logically shifts 32-bit mask right.
kshiftrq KSHIFTRQ k1, k2, imm8 EVEX AVX-512BW Logically shifts 64-bit mask right.
kshiftrw KSHIFTRW k1, k2, imm8 EVEX AVX-512F Logically shifts 16-bit mask right.
ktestb KTESTB k1, k2 EVEX AVX-512DQ ANDs 8-bit masks and sets EFLAGS (ZF/CF).
ktestd KTESTD k1, k2 EVEX AVX-512BW ANDs 32-bit masks and sets EFLAGS (ZF/CF).
ktestq KTESTQ k1, k2 EVEX AVX-512BW ANDs 64-bit masks and sets EFLAGS (ZF/CF).
ktestw KTESTW k1, k2 EVEX AVX-512F ANDs 16-bit masks and sets EFLAGS (ZF/CF).
kunpckbw KUNPCKBW k1, k2, k3 EVEX AVX-512 Interleaves 8-bit masks into 16-bit mask.
kunpckdq KUNPCKDQ k1, k2, k3 EVEX AVX-512BW Interleaves 32-bit masks into 64-bit mask.
kunpckwd KUNPCKWD k1, k2, k3 EVEX AVX-512BW Interleaves 16-bit masks into 32-bit mask.
kxorb KXORB k1, k2, k3 EVEX AVX-512DQ Bitwise XOR of 8-bit masks.
kxord KXORD k1, k2, k3 EVEX AVX-512BW Bitwise XOR of 32-bit masks.
kxorq KXORQ k1, k2, k3 EVEX AVX-512BW Bitwise XOR of 64-bit masks.
kxorw KXORW k1, k2, k3 EVEX AVX-512 Bitwise XOR of 16-bit masks.
lahf LAHF Legacy Base Loads bits 0, 2, 4, 6, and 7 of EFLAGS into AH.
lar LAR r, r/m16 System System Reads access rights from segment descriptor.
lddqu LDDQU xmm1, m128 SSE3 SSE3 Loads unaligned data avoiding split-line penalties.
ldmxcsr LDMXCSR m32 SSE SSE Loads the MXCSR control/status register from memory.
lds LDS r, m Legacy Base (Legacy) Loads pointer into DS and register.
ldtilecfg LDTILECFG m512 VEX AMX-TILE Loads AMX tile configuration from memory.
lea LEA r, m Legacy Base Computes effective address and stores in register.
leave LEAVE Legacy Base Releases stack frame (MOV ESP, EBP; POP EBP).