x86 Opcode Map
Reverse lookup instructions by their hexadecimal encoding.
| Opcode | Mnemonic | Syntax | Format | Name |
|---|---|---|---|---|
| EVEX.512.66.0F3A.W0 50 /r ib | vrangeps | VRANGEPS zmm1 {k1}, zmm2, zmm3/m512, imm8 | EVEX | Range Restriction Calculation Packed Single |
| EVEX.LLIG.66.0F3A.W0 51 /r | vrangess | VRANGESS xmm1 {k1}, xmm2, xmm3/m32, imm8 | EVEX | Range Restriction Calculation Scalar Single |
| EVEX.512.66.0F38.W0 4C /r | vrcp14ps | VRCP14PS zmm1 {k1}, zmm2/m512 | EVEX | Compute Approximate Reciprocal (14-bit) |
| EVEX.512.66.0F3A.W0 56 /r ib | vreduceps | VREDUCEPS zmm1 {k1}, zmm2/m512, imm8 | EVEX | Perform Reduction Transformation Packed Single |
| EVEX.LLIG.66.0F3A.W0 57 /r /ib | vreducess | VREDUCESS xmm1 {k1}, xmm2, xmm3/m32, imm8 | EVEX | Perform Reduction Transformation Scalar Single |
| EVEX.512.66.0F3A.W1 09 /r ib | vrndscalepd | VRNDSCALEPD zmm1 {k1}, zmm2/m512, imm8 | EVEX | Round Packed Double-Precision Floating-Point with Scale |
| EVEX.512.66.0F38.W0 4E /r | vrsqrt14ps | VRSQRT14PS zmm1 {k1}, zmm2/m512 | EVEX | Compute Approximate Reciprocal Square Root (14-bit) |
| EVEX.512.66.0F38.W1 2C /r | vscalefpd | VSCALEFPD zmm1 {k1}, zmm2, zmm3/m512 | EVEX | Scale Packed Float64 Values with Float64 Exponents |
| EVEX.512.66.0F38.W1 A2 /vsib | vscatterdpd | VSCATTERDPD [base+zmm_idx*scale] {k1}, zmm1 | EVEX | Scatter Packed Double Precision |
| EVEX.512.66.0F38.W0 A2 /vsib | vscatterdps | VSCATTERDPS [base+zmm_idx*scale] {k1}, zmm1 | EVEX | Scatter Packed Single Precision |
| EVEX.512.66.0F38.W1 C6 /5 /vsib | vscatterpf0dpd | VSCATTERPF0DPD {k1}, [base+ymm_idx] | EVEX | Scatter Prefetch Packed Double (L1) |
| EVEX.512.66.0F38.W0 C6 /5 /vsib | vscatterpf0dps | VSCATTERPF0DPS {k1}, [base+zmm_idx] | EVEX | Scatter Prefetch Packed Single (L1) |
| EVEX.512.66.0F38.W1 C7 /5 /vsib | vscatterpf0qpd | VSCATTERPF0QPD {k1}, [base+zmm_idx] | EVEX | Scatter Prefetch Packed Double (L1, Qword Indices) |
| EVEX.512.66.0F38.W0 C7 /5 /vsib | vscatterpf0qps | VSCATTERPF0QPS {k1}, [base+zmm_idx] | EVEX | Scatter Prefetch Packed Single (L1, Qword Indices) |
| EVEX.512.66.0F38.W1 A3 /vsib | vscatterqpd | VSCATTERQPD [base+zmm_idx*scale] {k1}, zmm1 | EVEX | Scatter Packed Double Precision (Quadword Indices) |
| EVEX.512.66.0F38.W0 A3 /vsib | vscatterqps | VSCATTERQPS [base+zmm_idx*scale] {k1}, zmm1 | EVEX | Scatter Packed Single Precision (Quadword Indices) |
| VEX.256.F2.0F38.W0 CC 11:rrr:bbb | vsha512msg1 | VSHA512MSG1 ymm1, xmm2 | EVEX | SHA512 Message Schedule 1 |
| VEX.256.F2.0F38.W0 CD 11:rrr:bbb | vsha512msg2 | VSHA512MSG2 ymm1, ymm2 | EVEX | SHA512 Message Schedule 2 |
| VEX.256.F2.0F38.W0 CB 11:rrr:bbb | vsha512rnds2 | VSHA512RNDS2 ymm1, ymm2, xmm3 | EVEX | SHA512 Rounds 2 |
| EVEX.256.66.0F3A.W0 23 /r ib | vshuff32x4 | VSHUFF32X4 zmm1 {k1}, zmm2, zmm3/m512, imm8 | EVEX | Shuffle Packed Float32x4 |
| VEX.128.NP.0F38.W0 DA /r | vsm3msg1 | VSM3MSG1 xmm1, xmm2, xmm3 | VEX | SM3 Message Schedule 1 |
| VEX.128.66.0F3A.W0 DE /r /ib | vsm3rnds2 | VSM3RNDS2 xmm1, xmm2, imm8 | VEX | SM3 Rounds 2 |
| VEX.128.F3.0F38.W0 DA /r | vsm4key4 | VSM4KEY4 xmm1, xmm2, xmm3/m128 | VEX | SM4 Key Generation |
| VEX.128.F2.0F38.W0 DA /r | vsm4rnds4 | VSM4RNDS4 xmm1, xmm2, xmm3/m128 | VEX | SM4 Four Rounds Encryption |
| EVEX.512.NP.MAP5.W0 51 /r | vsqrtph | VSQRTPH zmm1 {k1}, zmm2/m512 | EVEX | Square Root Packed FP16 Values |
| EVEX.LLIG.F3.MAP5.W0 51 /r | vsqrtsh | VSQRTSH xmm1 {k1}, xmm2/m16 | EVEX | Square Root Scalar Half-Precision |
| EVEX.512.NP.MAP5.W0 5C /r | vsubph | VSUBPH zmm1 {k1}, zmm2, zmm3/m512 | EVEX | Subtract Packed FP16 Values |
| EVEX.LLIG.F3.MAP5.W0 5C /r | vsubsh | VSUBSH xmm1 {k1}, xmm2, xmm3/m16 | EVEX | Subtract Scalar Half-Precision |
| VEX.128.66.0F38.W0 0F /r | vtestpd | VTESTPD xmm1, xmm2/m128 | AVX | Packed Bit Test Double-Precision |
| VEX.128.66.0F38.W0 0E /r | vtestps | VTESTPS xmm1, xmm2/m128 | AVX | Packed Bit Test Single-Precision |
| VEX.256.0F.WIG 77 | vzeroall | VZEROALL | VEX | Zero All YMM Registers |
| VEX.128.0F.WIG 77 | vzeroupper | VZEROUPPER | VEX | Zero Upper Bits of YMM Registers |
| 9B | wait | WAIT | Legacy | Wait |
| 0F 09 | wbinvd | WBINVD | System | Write Back and Invalidate Cache |
| F3 0F 09 | wbnoinvd | WBNOINVD | Legacy | Write Back and Do Not Invalidate Cache |
| F3 0F AE /2 | wrfsbase | WRFSBASE r64 | Legacy | Write FS Base |
| F3 0F AE /3 | wrgsbase | WRGSBASE r64 | Legacy | Write GS Base |
| 0F 30 | wrmsr | WRMSR | System | Write Model Specific Register |
| NP 0F 01 EF | wrpkru | WRPKRU | Legacy | Write Protection Key Rights |
| C6 F8 | xabort | XABORT imm8 | Legacy | Transaction Abort |
| 0F C1 | xadd | XADD r/m, r | Legacy | Exchange and Add |
| C7 F8 | xbegin | XBEGIN rel | Legacy | Transaction Begin |
| 87 | xchg | XCHG r/m, r | Legacy | Exchange Register/Memory with Register |
| NP 0F 01 D5 | xend | XEND | Legacy | Transaction End |
| NP 0F 01 D0 | xgetbv | XGETBV | Legacy | Get Value of Extended Control Register |
| D7 | xlat | XLAT m8 | Legacy | Table Look-up Translation |
| 31 | xor | XOR r/m, r | Legacy | Logical Exclusive OR |
| NP 0F 57 /r | xorps | XORPS xmm, xmm/m128 | SSE | Bitwise Logical XOR Packed Single-Precision |
| NP 0F AE /5 | xrstor | XRSTOR m | Legacy | Restore Processor Extended States |
| NP 0F C7 /3 | xrstors | XRSTORS m | Legacy | Restore Supervisor States |
| NP 0F AE /4 | xsave | XSAVE m | Legacy | Save Processor Extended States |
| NP 0F C7 /4 | xsavec | XSAVEC m | Legacy | Save Processor Extended States with Compaction |
| NP 0F AE /6 | xsaveopt | XSAVEOPT m | Legacy | Save Processor Extended States Optimized |
| NP 0F C7 /5 | xsaves | XSAVES m | Legacy | Save Supervisor States |
| NP 0F 01 D1 | xsetbv | XSETBV | Legacy | Set Value of Extended Control Register |
| F2 0F 01 E8 | xsusldtrk | XSUSLDTRK | Legacy | Suspend Tracking Load Addresses |
| NP 0F 01 D6 | xtest | XTEST | Legacy | Test If In Transaction |