A32 (System) Instructions
36 ARM instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| cdp | CDP<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2> | Coprocessor | Initiates a coprocessor data processing operation. |
| cdp2 | CDP2<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2> | Coprocessor | Initiates a coprocessor operation (Extension encoding). |
| cps | CPS<effect> <iflags> {, #<mode>} | System | Changes the processor mode or interrupt masks. |
| dcps1 | DCPS1 | System | Switches execution to EL1 (Debug). |
| dcps2 | DCPS2 | System | Switches execution to EL2 (Debug). |
| dcps3 | DCPS3 | System | Switches execution to EL3 (Debug). |
| eret | ERET | System | Returns from an exception (A32). |
| eret | ERET | Thumb System | Returns from an exception (Thumb state). |
| hvc | HVC #<imm> | System | Calls the Hypervisor (EL2). |
| ldc | LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | Loads memory into a coprocessor. |
| ldc2 | LDC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | Loads memory into a coprocessor (Extension encoding). |
| mcr | MCR<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | Writes a general-purpose register to a coprocessor register (e.g., CP15). |
| mcr2 | MCR2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | Writes a general-purpose register to a coprocessor (Extension encoding). |
| mcrr | MCRR<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | Writes two general-purpose registers to a coprocessor (64-bit transfer). |
| mcrr2 | MCRR2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | Writes two registers to a coprocessor (Extension encoding). |
| mrc | MRC<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | Reads a coprocessor register into a general-purpose register. |
| mrc2 | MRC2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | Reads a coprocessor register into a general-purpose register (Extension encoding). |
| mrrc | MRRC<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | Reads a coprocessor register into two general-purpose registers. |
| mrrc2 | MRRC2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | Reads a coprocessor register into two registers (Extension encoding). |
| mrs | MRS <Rd>, <banked_reg> | System | Reads a banked register into a general-purpose register. |
| mrs | MRS <Rd>, <spec_reg> | Thumb System | Read special register (Thumb). |
| mrs | MRS<c> <Rd>, <spec_reg> | System | Reads CPSR or SPSR. |
| msr | MSR <banked_reg>, <Rn> | System | Writes to a banked register from a general-purpose register. |
| msr | MSR <spec_reg>, #<imm> | System | Writes an immediate to a status register (A32). |
| msr | MSR <spec_reg>, <Rn> | Thumb System | Write special register (Thumb). |
| msr | MSR<c> <spec_reg>_<fields>, <Rn> | System | Writes to CPSR or SPSR. |
| pld | PLD [<Rn>, #<imm>] | Load/Store | Hints memory system to bring data into cache. |
| pli | PLI [<Rn>, #<imm>] | Load/Store | Hints memory system to bring instructions into cache. |
| rfe | RFE<c> <Rn>{!} | System | Loads PC and CPSR from the stack. |
| setend | SETEND <endian> | System | Sets the endianness for data accesses (BE/LE). |
| setpan | SETPAN #<imm> | System | Enables/Disables PAN (Prevents kernel accessing user memory). |
| smc | SMC<c> #<imm> | System | Calls the Secure Monitor (EL3). |
| srs | SRS<c> SP{!}, #<mode> | System | Stores LR and SPSR to the stack of a specific mode. |
| stc | STC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | Stores coprocessor contents to memory. |
| stc2 | STC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | Stores coprocessor contents to memory (Extension encoding). |
| svc | SVC<c> #<imm> | System | System call (formerly SWI). |