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RISC-V Opcode Map

Reverse lookup instructions by their hexadecimal encoding.

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Opcode Mnemonic Syntax Format Name
0x3C006057 VSLIDE1DOWN.VX VSLIDE1DOWN.VX vd, vs2, rs1, vm OPIVX Vector Slide One Element Down
0x38006057 VSLIDE1UP.VX VSLIDE1UP.VX vd, vs2, rs1, vm OPIVX Vector Slide One Element Up
0x3C003057 VSLIDEDOWN.VI VSLIDEDOWN.VI vd, vs2, imm, vm OPIVI Vector Slide Down Immediate
0x3C004057 VSLIDEDOWN.VX VSLIDEDOWN.VX vd, vs2, rs1, vm OPIVX Vector Slide Down
0x38003057 VSLIDEUP.VI VSLIDEUP.VI vd, vs2, imm, vm OPIVI Vector Slide Up Immediate
0x38004057 VSLIDEUP.VX VSLIDEUP.VX vd, vs2, rs1, vm OPIVX Vector Slide Up
0x94003057 VSLL.VI VSLL.VI vd, vs2, imm, vm OPIVI Vector Shift Left Logical Immediate
0x94000057 VSLL.VV VSLL.VV vd, vs2, vs1, vm OPIVV Vector Shift Left Logical
0x02B00027 VSM.V VSM.V vs3, (rs1) VS-Type Vector Store Mask
0x9C000057 VSMUL.VV VSMUL.VV vd, vs2, vs1, vm OPIVV Vector Single-Width Saturating Multiply
0x0C006027 VSOXEI32.V VSOXEI32.V vs3, (rs1), vs2, vm VS-Type Vector Store Ordered Indexed (32-bit indices)
0xA4003057 VSRA.VI VSRA.VI vd, vs2, imm, vm OPIVI Vector Shift Right Arithmetic Immediate
0xA4000057 VSRA.VV VSRA.VV vd, vs2, vs1, vm OPIVV Vector Shift Right Arithmetic
0xA0003057 VSRL.VI VSRL.VI vd, vs2, imm, vm OPIVI Vector Shift Right Logical Immediate
0xA0000057 VSRL.VV VSRL.VV vd, vs2, vs1, vm OPIVV Vector Shift Right Logical
0x08006027 VSSE32.V VSSE32.V vs3, (rs1), rs2, vm VS-Type Vector Store Strided Element (32-bit)
0x20005027 VSSEG2E16.V VSSEG2E16.V vs3, (rs1), vm VS-Type Vector Store Segment (2 fields, 16-bit)
0x40000027 VSSEG3E8.V VSSEG3E8.V vs3, (rs1), vm VS-Type Vector Store Segment (3 fields, 8-bit)
0x60000027 VSSEG4E8.V VSSEG4E8.V vs3, (rs1), vm VS-Type Vector Store Segment (4 fields, 8-bit)
0xAC000057 VSSRA.VV VSSRA.VV vd, vs2, vs1, vm OPIVV Vector Saturating Shift Right Arithmetic
0xA8000057 VSSRL.VV VSSRL.VV vd, vs2, vs1, vm OPIVV Vector Saturating Shift Right Logical
0x8C000057 VSSUB.VV VSSUB.VV vd, vs2, vs1, vm OPIVV Vector Saturating Integer Subtract
0x88000057 VSSUBU.VV VSSUBU.VV vd, vs2, vs1, vm OPIVV Vector Saturating Integer Subtract Unsigned
0x08000057 VSUB.VV VSUB.VV vd, vs2, vs1, vm OPIVV Vector Integer Subtract
0x04006027 VSUXEI32.V VSUXEI32.V vs3, (rs1), vs2, vm VS-Type Vector Store Unordered Indexed (32-bit indices)
0xC4002057 VWADD.VV VWADD.VV vd, vs2, vs1, vm OPIVV Vector Widening Integer Add
0xC0002057 VWADDU.VV VWADDU.VV vd, vs2, vs1, vm OPIVV Vector Widening Integer Add Unsigned
0xF4002057 VWMACC.VV VWMACC.VV vd, vs1, vs2, vm OPIVV Vector Widening Multiply-Accumulate
0xFC002057 VWMACCSU.VV VWMACCSU.VV vd, vs1, vs2, vm OPIVV Vector Widening MAC (Signed * Unsigned)
0xF0002057 VWMACCU.VV VWMACCU.VV vd, vs1, vs2, vm OPIVV Vector Widening Multiply-Accumulate Unsigned
0xF8006057 VWMACCUS.VX VWMACCUS.VX vd, rs1, vs2, vm OPIVV Vector Widening MAC (Unsigned * Signed)
0xEC002057 VWMUL.VV VWMUL.VV vd, vs2, vs1, vm OPIVV Vector Widening Integer Multiply
0xC4000057 VWREDSUM.VS VWREDSUM.VS vd, vs2, vs1, vm OPMVV Vector Widening Reduction Sum Signed
0xC0000057 VWREDSUMU.VS VWREDSUMU.VS vd, vs2, vs1, vm OPMVV Vector Widening Reduction Sum Unsigned
0xD4003057 VWSLL.VI VWSLL.VI vd, vs2, imm, vm OPIVI Vector Widening Shift Left Logical Immediate
0xD4000057 VWSLL.VV VWSLL.VV vd, vs2, vs1, vm OPIVV Vector Widening Shift Left Logical
0xD4004057 VWSLL.VX VWSLL.VX vd, vs2, rs1, vm OPIVX Vector Widening Shift Left Logical Scalar
0xCC002057 VWSUB.VV VWSUB.VV vd, vs2, vs1, vm OPIVV Vector Widening Integer Subtract
0x2C003057 VXOR.VI VXOR.VI vd, vs2, imm, vm OPIVI Vector XOR Immediate
0x2C000057 VXOR.VV VXOR.VV vd, vs2, vs1, vm OPIVV Vector Bitwise XOR
0x10500073 WFI WFI R-Type (System) Wait for Interrupt
0x00D00073 WRS.NTO WRS.NTO I-Type Wait on Reservation Set (Normal Time-Out)
0x01D00073 WRS.STO WRS.STO I-Type Wait on Reservation Set (Short Time-Out)
0x40004033 XNOR XNOR rd, rs1, rs2 R-Type Exclusive NOR
0x00004033 XOR XOR rd, rs1, rs2 R-Type Logical XOR
0x00004013 XORI XORI rd, rs1, imm I-Type Logical XOR Immediate
0x0800403B ZEXT.H ZEXT.H rd, rs1 I-Type Zero Extend Halfword