v_pk_minimum3_f16 GPU Native ISA AMD Vector

Vector Packed Arithmetic

v_pk_minimum3_f16

Select the component-wise IEEE minimum() of three half-precision float inputs and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OPSEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
11001100
31:24
00110110
23:16
CLAMP
15
OPSEL_HI[2]
14
OPSEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 54 in OP rebuilds 0x00000000CC360000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 27, field layout).

Format VOP3P
Width 64 bits
Opcode 54
Identifier 0x00000000CC360000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16-bit half-precision floating point value. Packed 2-component value. (OPR_VGPR, FMT_NUM_PK2_F16)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_F16)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_F16)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Sources