v_smfmac_f32_16x16x128_bf8_fp8 GPU Native ISA AMD Matrix

Vector Packed Arithmetic

v_smfmac_f32_16x16x128_bf8_fp8

Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored…

Encoding

Binary Layout (AMD CDNA 4)
BLGP
63:61
ACC
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
0111100
22:16
ACC_CD
15
ABID
14:11
CBSZ
10:8
VDST
7:0
 

The VOP3P_MFMA layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 60 in OP rebuilds 0x00000000D3BC0000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP3P
Width 64 bits
Opcode 60
Identifier 0x00000000D3BC0000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_PK4_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_PK16_BF8)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_PK32_FP8)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the VOP3P_MFMA encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply the 16x128 sparse matrix in the first input by the 128x16 matrix in the second input and accumulate the result into the 16x16 matrix stored in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.

Sources