v_pk_mov_b32 GPU Native ISA AMD Vector

Vector Packed Arithmetic

v_pk_mov_b32

Move data from two vector inputs into two vector registers.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OP_SEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
0110011
22:16
CLAMP
15
OP_SEL_HI[2]
14
OP_SEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 51 in OP rebuilds 0x00000000D3B30000, an identifier AMD lists for this encoding. The same in the other 2 generations that define it.

Format VOP3P
Width 64 bits
Opcode 51
Identifier 0x00000000D3B30000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_PK2_B32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_PK2_B32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_PK2_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

The source operands are treated as 64 bit and are subject to alignment restrictions for both SGPR and VGPR. For two VGPR inputs this opcode can be used as an arbitrary gather by using OP_SEL to select either the even VGPR specified or the next odd VGPR. v_pk_mov_b32 v0, v2, v4 op_sel:[0,1] // evaluates v0 <- v2 and v1 <- v5. Due to scalar broadcast restrictions if two SGPRs are specified as operands, they must be the same SGPR. v_pk_mov_b32 v0, s6, s6 op_sel:[0,1] // 64-bit move from scalar s[6:7].

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp0.u32 = S0.u32[OPSEL[0].i32 * 32 + 31 : OPSEL[0].i32 * 32]; tmp1.u32 = S1.u32[OPSEL[1].i32 * 32 + 31 : OPSEL[1].i32 * 32]; D0.u32[31 : 0] = tmp0.u32; D0.u32[63 : 32] = tmp1.u32

Sources