v_pk_mov_b32 GPU Native ISA AMD Vector

V PK MOV B32 Vector Packed Arithmetic

v_pk_mov_b32

Move data from two vector inputs into two vector registers.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3P) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3P
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

The source operands are treated as 64 bit and are subject to alignment restrictions for both SGPR and VGPR. For two VGPR inputs this opcode can be used as an arbitrary gather by using OP_SEL to select either the even VGPR specified or the next odd VGPR. v_pk_mov_b32 v0, v2, v4 op_sel:[0,1] // evaluates v0 <- v2 and v1 <- v5. Due to scalar broadcast restrictions if two SGPRs are specified as operands, they must be the same SGPR. v_pk_mov_b32 v0, s6, s6 op_sel:[0,1] // 64-bit move from scalar s[6:7].

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp0.u32 = S0.u32[OPSEL[0].i32 * 32 + 31 : OPSEL[0].i32 * 32]; tmp1.u32 = S1.u32[OPSEL[1].i32 * 32 + 31 : OPSEL[1].i32 * 32]; D0.u32[31 : 0] = tmp0.u32; D0.u32[63 : 32] = tmp1.u32

Sources