v_pk_mad_i16 GPU Native ISA AMD Vector

Vector Packed Arithmetic

v_pk_mad_i16

Multiply two packed signed 16-bit integer inputs component-wise, add a packed signed 16-bit integer value from a third input component-wise, and…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OPSEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
11001100
31:24
00000000
23:16
CLAMP
15
OPSEL_HI[2]
14
OPSEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 0 in OP rebuilds 0x00000000CC000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (field layout), AMD CDNA 3 (field layout), AMD CDNA 2 (field layout), AMD CDNA 1 (field layout), AMD RDNA 4 (field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout).

Format VOP3P
Width 64 bits
Opcode 0
Identifier 0x00000000CC000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Signed 16-bit integral data. Packed 2-component value. (OPR_VGPR, FMT_NUM_PK2_I16)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 16-bit integral data. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_I16)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 16-bit integral data. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_I16)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 16-bit integral data. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two packed signed 16-bit integer inputs component-wise, add a packed signed 16-bit integer value from a third input component-wise, and store the result into a vector register.

Semantics

declare tmp : 32'B; tmp[15 : 0].i16 = S0[15 : 0].i16 * S1[15 : 0].i16 + S2[15 : 0].i16; tmp[31 : 16].i16 = S0[31 : 16].i16 * S1[31 : 16].i16 + S2[31 : 16].i16; D0.b32 = tmp

Example

v_pk_mad_i16 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources