v_pk_add_f32 GPU Native ISA AMD Vector
V PK ADD F32 Vector Packed Arithmetic
v_pk_add_f32
Add two packed single-precision float inputs component-wise and store the result into a vector register. No carry-in or carry-out support.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3P)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector Packed Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
declare tmp : 64'B;
tmp[31 : 0].f32 = S0[31 : 0].f32 + S1[31 : 0].f32;
tmp[63 : 32].f32 = S0[63 : 32].f32 + S1[63 : 32].f32;
D0.b64 = tmp
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 271.