v_pk_add_f32 GPU Native ISA AMD Vector

Vector Packed Arithmetic

v_pk_add_f32

Add two packed single-precision float inputs component-wise and store the result into a vector register. No carry-in or carry-out support.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OPSEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
11001100
31:24
00101001
23:16
CLAMP
15
OPSEL_HI[2]
14
OPSEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 41 in OP rebuilds 0x00000000CC290000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 50, field layout), AMD CDNA 3 (opcode 50, field layout), AMD CDNA 2 (opcode 50, field layout).

Format VOP3P
Width 64 bits
Opcode 41
Identifier 0x00000000CC290000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. Packed 2-component value. (OPR_VGPR, FMT_NUM_PK2_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_F32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

declare tmp : 64'B; tmp[31 : 0].f32 = S0[31 : 0].f32 + S1[31 : 0].f32; tmp[63 : 32].f32 = S0[63 : 32].f32 + S1[63 : 32].f32; D0.b64 = tmp

Sources