v_pk_lshlrev_b16 GPU Native ISA AMD Vector
V PK LSHLREV B16 Vector Packed Arithmetic
v_pk_lshlrev_b16
Given a packed shift count in the first vector input, calculate the component-wise logical shift left of the second packed vector input and store the…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3P)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Vector Packed Arithmetic
Reference
AMDGPU / GFX ISA
Description
Given a packed shift count in the first vector input, calculate the component-wise logical shift left of the second packed vector input and store the result into a vector register.
Semantics
tmp[31 : 16].u16 = (S1[31 : 16].u16 << S0.u32[19 : 16].u32);
tmp[15 : 0].u16 = (S1[15 : 0].u16 << S0.u32[3 : 0].u32);
D0.b32 = tmp.b32
Example
v_pk_lshlrev_b16 v5, s1, s2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 263. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project