v_pk_min_f16 GPU Native ISA AMD Vector

Vector Packed Arithmetic

v_pk_min_f16

Select the component-wise minimum of two packed half-precision float inputs and store the result into a vector register.

Also written as v_pk_min_num_f16. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OP_SEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
0010001
22:16
CLAMP
15
OP_SEL_HI[2]
14
OP_SEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 17 in OP rebuilds 0x00000000D3910000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP3P
Width 64 bits
Opcode 17
Identifier 0x00000000D3910000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_PK2_F16)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_PK2_F16)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_PK2_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

declare tmp : 32'B; tmp[15 : 0].f16 = v_min_f16(S0[15 : 0].f16, S1[15 : 0].f16); tmp[31 : 16].f16 = v_min_f16(S0[31 : 16].f16, S1[31 : 16].f16); D0.b32 = tmp

Example

v_pk_min_f16 v5, s1, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources