flat_load_dword GPU Native ISA AMD Vector

FLAT LOAD DWORD Flat Memory

flat_load_dword VDST, VADDR

Load one 32-bit dword per lane through the flat (generic) address space, resolved to global/scratch/LDS at runtime.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (FLAT) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format FLAT
Width 32 bits
Execution Unit Vector Memory Unit
Register Classes VGPR
Memory Segment flat/generic

Operands

  • VDST
    Destination VGPR
  • VADDR
    Per-lane 64-bit generic address (VGPR pair)

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Global-Memory Load ↗
equivalent with restrictions
ld (PTX)

Related

More in Flat Memory

Reference

AMDGPU / GFX ISA

Description

Load 32 bits of data from the flat aperture into a vector register.

Semantics

VDST[lane] = *(VADDR[lane]) for each active lane; the memory aperture (global, scratch, or LDS) is determined per-address at runtime rather than fixed by the instruction.

Example

flat_load_dword  v2, v[0:1]   // v2 = *(v[0:1]), aperture resolved at runtime

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources