flat_load_dwordx3 GPU Native ISA AMD Vector
FLAT LOAD DWORDX3 Flat Memory
flat_load_dwordx3
Load 96 bits of data from the flat aperture into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (FLAT)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Flat Memory
Reference
AMDGPU / GFX ISA
Semantics
addr = CalcFlatAddr(ADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32;
VDATA[95 : 64] = MEM[addr + 8U].b32
Example
flat_load_dwordx3 v[5:7], v[1:2]A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 483. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project