flat_load_sshort GPU Native ISA AMD Vector

Flat Memory

flat_load_sshort

Load 16 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register.

Also written as flat_load_i16. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (FLAT) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format FLAT

Operands

  • VDST
    Written. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)
  • ADDR
    Read. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_FLAT encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Flat Memory

Reference

AMDGPU / GFX ISA

Semantics

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32); VDATA.i32 = 32'I(signext(MEM[addr].i16))

Example

flat_load_sshort v5, v[1:2]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources