flat_load_d16_i8 GPU Native ISA AMD Vector

Flat Memory

flat_load_d16_i8

Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.

Also written as flat_load_sbyte_d16. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
unassigned
63
VSRC
62:55
TH
54:52
SCOPE
51:50
SVE
49
SCALE_OFFSET
48
unassigned
47:40
VDST
39:32
11101100
31:24
unassigned
23:22
00011111
21:14
unassigned
13:8
NV
7
SADDR
6:0
 

The ENC_VFLAT layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 31 in OP rebuilds 0x0000000000000000EC07C000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 4 (field layout), AMD RDNA 3.5 (layout not verifiable), AMD RDNA 3 (layout not verifiable).

Format FLAT
Width 96 bits
Opcode 31
Identifier 0x0000000000000000EC07C000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. Any scalar GPR operand including VCC and NULL. Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VFLAT encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Flat Memory

Reference

AMDGPU / GFX ISA

Example

flat_load_d16_i8 v5, v[1:2]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources