flat_atomic_smin_x2 GPU Native ISA AMD Vector

Flat Memory

flat_atomic_smin_x2

Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture.

Also written as flat_atomic_min_i64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (FLAT) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format FLAT

Operands

  • VDST
    Written. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)
  • ADDR
    Read. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • DATA
    Read. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_FLAT encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Flat Memory

Reference

AMDGPU / GFX ISA

Description

Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the SC0 bit is set.

Semantics

addr = CalcFlatAddr(ADDR.b32, OFFSET.b32); tmp = MEM[addr].i64; src = DATA.i64; MEM[addr].i64 = src < tmp ? src : tmp; RETURN_DATA.i64 = tmp

Example

flat_atomic_smin_x2 v[1:2], v[2:3]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources