flat_atomic_max_f32 GPU Native ISA AMD Vector

FLAT ATOMIC MAX F32 Flat Memory

flat_atomic_max_f32

Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (FLAT) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format FLAT
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Flat Memory

Reference

AMDGPU / GFX ISA

Description

Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture. Update the flat aperture with the selected value. Store the original value from flat aperture into a vector register iff the GLC bit is set.

Example

flat_atomic_max_f32 v[1:2], v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources